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US4884126A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device having parallel-connected, self turn-off type semiconductor elements

Assignee: Hitachi Ltd
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Filing: 1988-01-15
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Granted: 1989-11-28
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Expires: 2008-01-15
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Abstract

Abstract A semiconductor device is disclosed in which at least two semiconductor elements each having a self turn-off function are disposed in a package and connected in paralllel, and in which the semiconductor elements, terminals mounted on the package, and internal wirings for connecting the semiconductor elements to the terminals are arranged in geometrical symmetry, to eliminate the imbalance of current between the semiconductor elements.

Inventors

  • 👤 Eiji Harada
  • 👤 Hitoshi Matsuzaki
  • 👤 Sigeo Tomita
  • 👤 Katsunori Chida

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 06:02
CPC Classifications
H; H10; H10W; H10W90/00

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 200 words
A semiconductor device having parallel-connected, self turn-off semiconductor elements, comprising: (a) a package for packaging self turn-off type semiconductor elements, said package including a metallic cooling fin, an insulating side case provided on one principal surface of said cooling fin, and an insulating covering case disposed on said side case; (b) a plurality of self turn-off type semiconductor elements each having a semiconductor chip having predetermined pn junctions therein and three electrodes in ohmic contact with said semiconductor chip, and mounted on said cooling fin of said package through an insulating material; and (c) a plurality of terminals mounted on said insulating covering case, each having one end disposed internally of said package and electrically connected with a respective electrode of a corresponding one of said plurality of self turn-off type elements, and the other end exposed externally of said package through said insulating covering case; and at least one of said plurality of terminals electrically connected with respective ones of said plurality of self turn-off semiconductor elements being mounted on a common terminal mount region of said insulating covering case, and said plurality of self turn-off semiconductor elements being disposed symmetrically with respect to said common terminal mount region.
Claim 2
Dependent Claim 200 words
A semiconductor device having parallel-connected, self turn-off semiconductor elements, comprising: (a) a package for packaging self turn-off type semiconductor elements, said package including a metallic cooling fin, an insulating side case provided on one principal surface of said cooling fin, and an insulating covering case disposed on said side case; (b) a plurality of self turn-off type semiconductor elements each having a semiconductor chip having predetermined pn junctions therein and three electrodes in ohmic contact with said semiconductor chip, and mounted on said cooling fin of said package through an insulating material; and (c) a plurality of terminals mounted on said insulating covering case, each having one end disposed internally of said package and electrically connected with a respective electrode of a corresponding one of said plurality of self turn-off type elements, and the other end exposed externally of said package through said insulating covering case; and at least one of said plurality of terminals electrically connected with respective ones of said plurality of self turn-off semiconductor elements being mounted on a common terminal mount region of said insulating covering case, and said plurality of self turn-off semiconductor elements being disposed symmetrically with respect to said common terminal mount region.
Claim 3
Dependent Claim 26 words
A semiconductor device according to claim 1, wherein each of said self turn-off type semiconductor elements is one of a gate turn-off thyristor and a transistor.
Claim 4
Dependent Claim 21 words
A semiconductor device according to claim 1, wherein all of said plurality of terminals are mounted in said common mount region.
Claim 5
Dependent Claim 27 words
A semiconductor device according to claim 1, wherein each of said plurality of self turn-off semiconductor elements are one of a gate turn-off thyristor and a transistor.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-11-27 1993-05-29 1993-11-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-11-27 1997-05-29 1997-11-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-11-27 2001-05-29 2001-11-28 $7700.00 Window Closed / Lapsed

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