US4883993A
Expired / Lapsed
US
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Antibounce circuit for digital circuits
Assignee: STMicroelectronics SRL
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Filing: 1988-12-02
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Granted: 1989-11-28
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Expires: 2008-12-02
Abstract
Abstract The antibounce circuit comprises: (a) a first flip-flop constituted by a first and a second NAND gate (10, 12) having their respective outputs connected to one of the inputs of the other gate, the free input of the first gate being the input for said digital signal; (b) a second flip-flop constituted by a third and fourth NAND gate (14, 16) having their respective outputs connected to one of the inputs of the other gate, the free input of the third gate being connected to the output of the first gate; (c) a non-inverting delay circuit (20, 22, 24) connecting the output of the third gate to the free input of the second gate; (d) a first inverter connecting the output of the delay circuit to the free input of the fourth gate.
Inventors
- 👤 Pierangelo Confalonieri
- 👤 Sergio Pernici
- 👤 Germano Nicollini
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:53
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
140 words
Antibounce circuit for digital signals, characterized in that it comprises: (a) a first flip-flop constituted by a first and a second NAND gate (10, 12) having their respective outputs connected to one of the inputs of the other gate, the free input of the first gate being the input for said digital signal; (b) a second flip-flop constituted by a third and a fourth NAND gate (14, 16) having their respective outputs connected to one of the inputs of said other gate, the free input of said third gate being connected to the output of said first gate; (c) a non-inverting delay circuit (20, 22, 24) connecting the output of said third gate to the free input of said second gate; (d) a first inverter connecting the output of said delay circuit to the free input of said fourth gate.
Claim 2
Dependent Claim
140 words
Antibounce circuit for digital signals, characterized in that it comprises: (a) a first flip-flop constituted by a first and a second NAND gate (10, 12) having their respective outputs connected to one of the inputs of the other gate, the free input of the first gate being the input for said digital signal; (b) a second flip-flop constituted by a third and a fourth NAND gate (14, 16) having their respective outputs connected to one of the inputs of said other gate, the free input of said third gate being connected to the output of said first gate; (c) a non-inverting delay circuit (20, 22, 24) connecting the output of said third gate to the free input of said second gate; (d) a first inverter connecting the output of said delay circuit to the free input of said fourth gate.
Claim 3
Dependent Claim
32 words
Antibounce circuit according to claim 1, characterized in that a second inverter (26) is connected at the output of said third gate (14), its output constituting the output of the antibounce circuit.
Claim 4
Dependent Claim
54 words
Antibounce circuit according to claim 1, characterized in that said delay circuit comprises a pair of cascade coupled inverters (20, 22) and a capacitor (24) between their common node and the ground, the first inverter of said pair of inverters being resistive both towards the high power supply and towards the low power supply.
Claim 5
Dependent Claim
54 words
Antibounce circuit according to claim 1, characterized in that the switching threshold of said second gate (12) relatively to its input connected to the output of said first gate (10) is lower than the switching threshold of said third gate (14) relatively to its input connected to the output of said first gate (10).
Claim 6
Dependent Claim
41 words
Antibounce circuit according to claim 2, characterized in that the switching threshold of said fourth gate (16) relatively to its input connected to the output of said third gate (14) is lower than the switching threshold of said second inverter (26).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-27 | 1993-05-29 | 1993-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-27 | 1997-05-29 | 1997-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-27 | 2001-05-29 | 2001-11-28 | $7700.00 | Window Closed / Lapsed |