Interference suppression device for logic signals

Claim 1

An interference suppressing device for logic signals, comprising a first and second J-K-Master-Slave flip-flop having each complementary inputs J and K and complementary outputs Q and Q a clock input CLK and complementary reset inputs PR and CL respectively, the output terminals Q and Q of said first flipflop being connected to the inputs J and K respectively of said second flip-flop, an input terminal connected to the input J of said first flip-flop and an inverter connected between said input terminal and the other input K of said first flip-flop, an output terminal connected to the output Q of said second flip-flop, a first NAND-gate having at least two inputs one of said inputs being connected to the input J of said first flip-flop and at least one other input being connected to the corresponding output Q of said second flip-flop, said first NAND-gate having an output connected to the reset inputs PR of said first and second flipflops, and a second NAND-gate having at least two inputs with one of said inputs being connected to the input K of said first flipflop and with at least one other input being connected to the corresponding output Q of said second flip-flop, said second NAND-gate having an output connected to the reset inputs CL of said first and second flip-flops, and said clock inputs being connected to a source of clock pulses, a time interval equal to twice the period of the clock pulses being selected longer than the maximum expected duration of any interference signal.