Communication system

Claim 2

A first arrival preference circuit, provided in an apparatus having a processing device for receiving input signals and transmitting an output signal to other apparatus, said first arrival preference circuit comprising: two gate circuits connected respectively to each of two input terminals for receiving first and second input signals; a first arrival discrimination circuit for discriminating which one of the first and second input signals has arrived first to one or the other of said two input terminals and for determining that the first and second input signals have arrived to the two input terminals at the same time; a gate control circuit for causing the gate circuit connected to the input terminal where the first signal has arrived or to a predetermined one of said terminals when the two input signals have arrived at the same time to accept the input signal, and for causing the other gate circuit to be inhibited from accepting the input signal, and a sending control circuit for producing a non-sending signal while one of the first and second input signals is being accepted, the non-sending signal controlling said processing device to inhibit transmission of said output signal to said other apparatus.

Claim 3

A communication system comprising a plurality of devices interconnected into a loop by a transmission line, each of the devices being provided with two pairs of sending and receiving terminals for transmitting signals in directions different to the other devices immediately adjacent thereto on the loop by a pair of transmission channels serving as said transmission line and connected to the two pairs of sending and receiving terminals respectively, each of the transmission channels having a sending line and receiving line, wherein each of the devices is provided with a preference circuit comprising: a first arrival discrimination circuit having three input terminals and a signal output terminal providing a signal responsive to signals at said three input terminals wherein said first and second input terminals are connected respectively, to said two receiving terminals; a first flip-flop having an input connected to a first of said two receiving terminals; a second flip-flop having an input coupled to said signal output terminals of said arrival discrimination circuit; an OR circuit coupled to outputs of said first and second flip-flops; and third and fourth flip-flops having inputs connected, respectively, to outputs of said first and second flip-flops, an inverting output of said third flip-flop resetting said second flip-flop and an inverting of said fourth flip-flop resetting and first flip-flop and connected to said third input terminal of said first arrival discrimination circuit; an output of said OR gate providing an output signal from said first arrival preference circuit.

Claim 4

A communication system comprising a plurality of devices interconnected into a loop by a transmission line, each of the devices being provided with two pairs of sending and receiving terminals for transmitting signals in directions different to the other devices immediately adjacent thereto on the loop by a pair of transmission channels serving as said transmission line and connected to the two pairs of sending and receiving terminals respectively, each of the transmission channels having a sending line and receiving line, wherein each of the devices is provided with a preference circuit comprising: a first arrival discrimination circuit having three input terminals and a signal output terminal providing a signal responsive to signals at said three input terminals wherein said first and second input terminals are connected respectively, to said two receiving terminals; a first flip-flop having an input connected to a first of said two receiving terminals; a second flip-flop having an input coupled to said signal output terminals of said arrival discrimination circuit; an OR circuit coupled to outputs of said first and second flip-flops; and third and fourth flip-flops having inputs connected, respectively, to outputs of said first and second flip-flops, an inverting output of said third flip-flop resetting said second flip-flop and an inverting of said fourth flip-flop resetting and first flip-flop and connected to said third input terminal of said first arrival discrimination circuit; an output of said OR gate providing an output signal from said first arrival preference circuit.

Claim 5

A communication system as defined in claim 2 wherein said first arrival discrimination circuit comprises: a first AND gate having one input connected to said first and a third arrival discrimination circuit input terminal; an inverter having an input connected to said second arrival discrimination circuit input terminal; a second AND gate having a first inverting input connected to an output of said first AND gate and having a second inverting input connected to an output of said inverter and having an output connected to said output terminal of said first arrival discrimination circuit.

Claim 6

A communication system comprising a plurality of processing devices, each said processing device receiving first and second input signals and transmitting an output signal to said devices interconnected into a loop by a transmission line, each of said devices being provided with two pairs of sending and receiving terminals for transmitting said output signals in different directions to other ones of said devices immediately adjacent thereto on the loop by a pair of transmission channels serving as said transmission line and connected to the two pairs of sending and receiving terminals, respectively, each of the transmission channels having a sending line and a receiving line wherein each said processing device is provided with a preference circuit, said first arrival preference circuit comprising: two gate circuits connected, respectively, to each of two input terminals for receiving first and second input signals; a first arrival discrimination circuit for discriminating which one or the other of the first and second input signals has arrived first to the two input terminals and for determining that the first and second input signals have arrived to the two input terminals at the same time; a gate control circuit for causing the gate circuit connected to the input terminal where the first signal has arrived or to a predetermined one of said terminals when the two input signals have arrived at the same time, to accept the input signal, and for causing the other gate circuit to be inhibited from accepting the input signal; and a sending control circuit for producing a non-sending signal while one of the first and second input signals is being accepted, the non-sending signal controlling said processing device to inhibit transmission of said output signal to said other devices.

Claim 7

A communication system comprising a plurality of processing devices, each said processing device receiving first and second input signals and transmitting an output signal to said devices interconnected into a loop by a transmission line, each of said devices being provided with two pairs of sending and receiving terminals for transmitting said output signals in different directions to other ones of said devices immediately adjacent thereto on the loop by a pair of transmission channels serving as said transmission line and connected to the two pairs of sending and receiving terminals, respectively, each of the transmission channels having a sending line and a receiving line wherein each said processing device is provided with a preference circuit, said first arrival preference circuit comprising: two gate circuits connected, respectively, to each of two input terminals for receiving first and second input signals; a first arrival discrimination circuit for discriminating which one or the other of the first and second input signals has arrived first to the two input terminals and for determining that the first and second input signals have arrived to the two input terminals at the same time; a gate control circuit for causing the gate circuit connected to the input terminal where the first signal has arrived or to a predetermined one of said terminals when the two input signals have arrived at the same time, to accept the input signal, and for causing the other gate circuit to be inhibited from accepting the input signal; and a sending control circuit for producing a non-sending signal while one of the first and second input signals is being accepted, the non-sending signal controlling said processing device to inhibit transmission of said output signal to said other devices.

Claim 8

A communication system as defined in claim 4 wherein the sending and receiving lines are optical fibers, and each of the devices has an electro/optic conversion circuit provided for each sending terminal thereof and an opto/electric conversion circuit provided for each receiving terminal thereof, the output side of the opto/electric conversion circuit of each pair being electrically connected to the input side of the electro-optic conversion circuit of the other pair.

Claim 9

A first arrival preference circuit as defined in claim 4 wherein said first arrival discrimination circuit comprises: said first AND gate having one input connected to said first and a third arrival discrimination circuit input terminal; an inverter having an input connected to said second arrival discrimination circuit input terminal; a second AND gate having a first inverting input connected to an output of said first AND gate and having a second inverting input connected to an output of said inverter and having an output connected to said output terminal of said first arrival discrimination circuit.

Claim 10

A first arrival preference circuit comprising: a first arrival discrimination circuit having three input terminals and a signal output terminal providing a signal responsive to signals at said three input terminals wherein first and second ones of said input terminals are connected, respectively, to two receiving terminals; a first flip-flop having an input connected to a first of said two receiving terminals; a second flip-flop having an input coupled to said signal output terminal of said first arrival discrimination circuit; an OR circuit coupled to outputs of said first and second flip-flops; and third and fourth flip-flops having inputs connected, respectively, to outputs of said first and second flip-flops, an inverting output of said third flip-flop resetting said second flip-flop and an inverting output of said fourth flip-flop resetting said first flip-flop and connected to said third input terminal of said first arrival discrimination circuit; an output of said OR gate providing an output signal from said first arrival preference circuit.

Claim 11

A first arrival preference circuit comprising: a first arrival discrimination circuit having three input terminals and a signal output terminal providing a signal responsive to signals at said three input terminals wherein first and second ones of said input terminals are connected, respectively, to two receiving terminals; a first flip-flop having an input connected to a first of said two receiving terminals; a second flip-flop having an input coupled to said signal output terminal of said first arrival discrimination circuit; an OR circuit coupled to outputs of said first and second flip-flops; and third and fourth flip-flops having inputs connected, respectively, to outputs of said first and second flip-flops, an inverting output of said third flip-flop resetting said second flip-flop and an inverting output of said fourth flip-flop resetting said first flip-flop and connected to said third input terminal of said first arrival discrimination circuit; an output of said OR gate providing an output signal from said first arrival preference circuit.