Patent US4882289A successfully refreshed from Google Patents.
US4882289A
Expired / Lapsed
US
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Method of making a semiconductor memory device with recessed array region
Assignee: Micron Memory Japan Ltd
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Filing: 1988-04-22
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Granted: 1989-11-21
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Expires: 2008-04-22
Abstract
Abstract A semiconductor memory wherein a memory cell region having a plurality of memory cells and has higher altitude from the surface of semiconductor substrate is formed in the recessed part of semiconductor substrate having the recessed part and projected part and a peripheral circuit region which is comparatively low from the surface of semiconductor substrate is formed to the projected part of semiconductor substrate.
Inventors
- 👤 Noboru Moriuchi
- 👤 Yoshiki Yamaguchi
- 👤 Toshihiko Tanaka
- 👤 Norio Hasegawa
- 👤 Yoshifumi Kawamoto
- 👤 Shin-Ichiro Kimura
- 👤 Toru Kaga
- 👤 Tokuo Kure
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:27
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; Y; Y10; Y10S; Y10S438/00; Y10S438/911
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
106 words
A method of manufacturing a semiconductor memory comprising the steps of: (a) selectively forming an oxidation-proof film to the first region of semiconductor substrate having the flat surface; (b) forming an oxide film to the second region other than the first region of said semiconductor substrate with said oxidation-proof film used as the mask; (c) forming a recessed part to the flat semiconductor substrate by removing an oxide film formed on said second region; (d) forming a memory cell region comprising a plurality of memory cells to said second region; and (e) forming a peripheral circuit region comprising a plurality of MISFETs to said first region.
Claim 2
Independent Claim
106 words
A method of manufacturing a semiconductor memory comprising the steps of: (a) selectively forming an oxidation-proof film to the first region of semiconductor substrate having the flat surface; (b) forming an oxide film to the second region other than the first region of said semiconductor substrate with said oxidation-proof film used as the mask; (c) forming a recessed part to the flat semiconductor substrate by removing an oxide film formed on said second region; (d) forming a memory cell region comprising a plurality of memory cells to said second region; and (e) forming a peripheral circuit region comprising a plurality of MISFETs to said first region.
Claim 3
Dependent Claim
40 words
A method of manufacturing a semiconductor memory according to claim 1, wherein said oxide film is a thermal oxide film and has the thickness almost equal to average altitude difference between said memory cell region and said peripheral circuit region.
Claim 4
Independent Claim
84 words
A method of manufacturing a semiconductor memory comprising the steps of: (a) selectively forming a dry-etching mask to a first region of a semiconductor substrate having flat surface; (b) forming a recessed part to said semiconductor substrate by dry etching of the second region not covered with the dry etching mask; (c) forming a memory cell array region comprising a plurality of memory cells to said second region; and (d) forming a peripheral circuit region having a plurality of MISFETs in said first region.
Claim 5
Independent Claim
84 words
A method of manufacturing a semiconductor memory comprising the steps of: (a) selectively forming a dry-etching mask to a first region of a semiconductor substrate having flat surface; (b) forming a recessed part to said semiconductor substrate by dry etching of the second region not covered with the dry etching mask; (c) forming a memory cell array region comprising a plurality of memory cells to said second region; and (d) forming a peripheral circuit region having a plurality of MISFETs in said first region.
Claim 6
Dependent Claim
62 words
A method of manufacturing a semiconductor memory according to claim 3 comprising the steps, between the steps (b) and (c), of: (e) removing said mask layer and forming an organic film on said first and second regions; and (f) removing said organic film by the etching forming gradual slope to the stepped portion at the boundary of said first and second regions.
Claim 7
Dependent Claim
39 words
A method of manufacturing a semiconductor memory according to claim 4 comprising, after the step (f), the steps of: (g) forming a thermal oxide film on the surface of said semiconductor substrate; and (h) removing said thermal oxide film.
Claim 8
Dependent Claim
28 words
A method of manufacturing a semiconductor memory according to claim 4, wherein said organic film shows the etching rate which is equal to that of said semiconductor substrate.
Claim 9
Dependent Claim
17 words
A method of manufacturing a semiconductor memory according to claim 6, wherein said organic film is photoresist.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-20 | 1993-05-22 | 1993-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-20 | 1997-05-22 | 1997-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-20 | 2001-05-22 | 2001-11-21 | $7700.00 | Window Closed / Lapsed |