US4642880A
Expired / Lapsed
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Method for manufacturing a recessed semiconductor device
Assignee: Toshiba Corp
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Filing: 1985-04-17
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Granted: 1987-02-17
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Expires: 2005-04-17
Abstract
Abstract A method for manufacturing a semiconductor device comprises a first step of forming a field insulation layer on a p-type semiconductor substrate and a second step of forming an n + -type region and n-type region in an element area surrounded by the field insulation layer. In particular, the second step includes a step of forming, in the element area, a recess having an inclined portion and flat bottom portion, a step of forming an SiO 2 film of a uniform thickness on the inclined portion and flat bottom portion, and a step of ion-implanting an n-type impurity into the substrate through the SiO 2 and effecting an annealing process.
Inventors
- 👤 Yoshihisa Mizutani
- 👤 Syunzi Yokogawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 01:26
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/608; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/0123; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13; Y; Y10; Y10S; Y10S148/00; Y10S148/082; Y10S148/085; Y10S438/00; Y10S438/978
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
105 words
A method for manufacturing a semiconductor device, comprising the steps of: (1) forming, in the surface area of a semiconductor substrate, a flat surface and an inclined surface adjacent said flat surface and at a predetermined angle thereto; (2) forming a covering layer of a uniform thickness on said flat and inclined surfaces; (3) implanting impurity ions into the substrate through said covering layer in a direction substantially perpendicular to said flat surface; and (4) annealing the ion-implanted substrate, thereby forming first and second regions of different impurity concentration below said flat and inclined surfaces, respectively, the impurity concentrations being dependent from the predetermined angle.
Claim 2
Independent Claim
105 words
A method for manufacturing a semiconductor device, comprising the steps of: (1) forming, in the surface area of a semiconductor substrate, a flat surface and an inclined surface adjacent said flat surface and at a predetermined angle thereto; (2) forming a covering layer of a uniform thickness on said flat and inclined surfaces; (3) implanting impurity ions into the substrate through said covering layer in a direction substantially perpendicular to said flat surface; and (4) annealing the ion-implanted substrate, thereby forming first and second regions of different impurity concentration below said flat and inclined surfaces, respectively, the impurity concentrations being dependent from the predetermined angle.
Claim 3
Dependent Claim
45 words
A method according to claim 1, wherein said step (1) includes a substep of forming a recess in the surface area of said substrate by anisotropically etching the substarate, said recess having said inclined surface as a side and said flate surface as a bottom.
Claim 4
Dependent Claim
26 words
A method according to claim 1, wherein said step (2) includes a substep of depositing silicon oxide on said flat and inclined surfaces by CVD process.
Claim 5
Dependent Claim
26 words
A method according to claim 1, wherein said step (2) includes a substep of depositing silicon nitride on said flat and inclined surfaces by CVD process.
Claim 6
Dependent Claim
28 words
A method according to claim 1, wherein said semiconductor substrate is formed of silicon, and said step (2) includes a substep of oxidizing said flat and inclined surfaces.
Claim 7
Dependent Claim
28 words
A method according to claim 1, wherein said semiconductor substrate is formed of silicon, and said step (2) includes a substep of nitriding said flat and inclined surfaces.
Claim 8
Independent Claim
162 words
A method for manufacturing a semiconductor device, comprising the steps of: (1) forming a field insulation layer on a semiconductor substrate of a first conductivity type of divide the surface area of said substrate into a plurality of element areas; (2) forming a recess in at least on of said element areas, said recess having a flat bottom and an inclined side; (3) forming a gate insulation layer on a part of said flat bottom and a gate electrode on said gate insulation layer; (4) forming a covering layer of uniform thickness on the flat bottom and inclined side; (5) implanting impurity ions of a second conductivity type into said element area through said covering layer in a direction substantially perpendicular to said flat bottom; and (6) annealing the ion-implanted substrate, thereby forming first and second regions as drain and source regions, respectively, below said flat bottom, sand a third region below said inclined side and in contact with said first region.
Claim 9
Independent Claim
162 words
A method for manufacturing a semiconductor device, comprising the steps of: (1) forming a field insulation layer on a semiconductor substrate of a first conductivity type of divide the surface area of said substrate into a plurality of element areas; (2) forming a recess in at least on of said element areas, said recess having a flat bottom and an inclined side; (3) forming a gate insulation layer on a part of said flat bottom and a gate electrode on said gate insulation layer; (4) forming a covering layer of uniform thickness on the flat bottom and inclined side; (5) implanting impurity ions of a second conductivity type into said element area through said covering layer in a direction substantially perpendicular to said flat bottom; and (6) annealing the ion-implanted substrate, thereby forming first and second regions as drain and source regions, respectively, below said flat bottom, sand a third region below said inclined side and in contact with said first region.
Claim 10
Dependent Claim
32 words
A method according to claim 7, wherein said step (2) includes a substep of forming said recess by anisotropically etching said element area with said field insultation layer used as a mask.
Claim 11
Dependent Claim
47 words
A method according to claim 8, further comprising a step (7) of forming a fourth region of said first conductivity type immediately below said field insulation layer in contact with said third region, said fourth region having a impurity concentration level higher than that of said substrate.
Claim 12
Dependent Claim
50 words
A method according to claim 9, wherein said step (4) includes a substep of forming said covering layer on the first gate electrode, flat bottom and inclined side, and which further comprises a step (8) of forming a second gate electrode over the first gate electrode through said covering layer.
Claim 13
Independent Claim
180 words
A method for manufacturing a semiconductor device, comprising the steps of: (1) forming a field insulation layer of a semiconductor substrate of a first conductivity type of divide the surface area of said substrate ino a plurality of element areas; (2) forming a recess in at least one of said element areas, said recess having first and second inclined sides and a flat bottom; (3) forming a gate insulation layer on a part of said flat bottom and gate electrode on said gate insulation layer; (4) forming a covering layer on the flat bottom and the first and second inclined sides with a uniform thickness; (5) implanting impurity ions of a second conductivity type into said element area through said covering layer in a direction substantially perpendicular to said flat bottom; and (6) annealing the ion-implanted substrate, thereby forming first and second regions as a drain and source below said flat bottom, a third region below said first inclined side in contact with said first region and fourth region below said second inclined side in contact with said second region.
Claim 14
Independent Claim
180 words
A method for manufacturing a semiconductor device, comprising the steps of: (1) forming a field insulation layer of a semiconductor substrate of a first conductivity type of divide the surface area of said substrate ino a plurality of element areas; (2) forming a recess in at least one of said element areas, said recess having first and second inclined sides and a flat bottom; (3) forming a gate insulation layer on a part of said flat bottom and gate electrode on said gate insulation layer; (4) forming a covering layer on the flat bottom and the first and second inclined sides with a uniform thickness; (5) implanting impurity ions of a second conductivity type into said element area through said covering layer in a direction substantially perpendicular to said flat bottom; and (6) annealing the ion-implanted substrate, thereby forming first and second regions as a drain and source below said flat bottom, a third region below said first inclined side in contact with said first region and fourth region below said second inclined side in contact with said second region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-16 | 1990-08-18 | 1991-02-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-16 | 1994-08-18 | 1995-02-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-16 | 1998-08-18 | 1999-02-17 | $7700.00 | Window Closed / Lapsed |