Method and apparatus for accelerated addition of sliced addends

Claim 1

A method for performing an addition operation on sliced addends in successive pipelined microinstructions, the addends having at least a more significant slice and a least significant slice, where the more significant slice in one of the addends in successive microinstructions is a zero in each said successive microinstruction, the method comprising the steps of: (a) monitoring first and second successive pipelined microinstructions in successive clock cycles to determine if both microinstructions are add operations; (b) detecting use of a destination of the first microinstruction as a source for the add operation of the second microinstruction; (c) requiring the more significant slice in at least one of the addends to be a zero in each said successive microinstruction; (d) performing said addition operations in each of said slices in said first microinstruction to calculate more and least significant slice sums and a more significant slice sum plus one; (f) upon a dermination that both microinstructions are add operations, and the detection of the use of the destination of the first microinstruction as a source for the add operation of the second microinstruction, pursuant to steps (a) and (b); (i) selecting the more significant slice sum of the first microinstruction to be the more significant slice sum of said second microinstruction when said carry-out is not detected; and (ii) selecting the more significant slice sum plus one to be the more significant slice sum of the second microinstruction when said carry-out is detected.

Claim 2

A method for performing an addition operation on sliced addends in successive pipelined microinstructions, the addends having at least a more significant slice and a least significant slice, where the more significant slice in one of the addends in successive microinstructions is a zero in each said successive microinstruction, the method comprising the steps of: (a) monitoring first and second successive pipelined microinstructions in successive clock cycles to determine if both microinstructions are add operations; (b) detecting use of a destination of the first microinstruction as a source for the add operation of the second microinstruction; (c) requiring the more significant slice in at least one of the addends to be a zero in each said successive microinstruction; (d) performing said addition operations in each of said slices in said first microinstruction to calculate more and least significant slice sums and a more significant slice sum plus one; (f) upon a dermination that both microinstructions are add operations, and the detection of the use of the destination of the first microinstruction as a source for the add operation of the second microinstruction, pursuant to steps (a) and (b); (i) selecting the more significant slice sum of the first microinstruction to be the more significant slice sum of said second microinstruction when said carry-out is not detected; and (ii) selecting the more significant slice sum plus one to be the more significant slice sum of the second microinstruction when said carry-out is detected.

Claim 4

An apparatus for performing an addition operation in a computer on sliced addends in successive microinstructions, the addends having at least a more significant slice and a least significant slice, where a more significant slice in one of the addends in successive microinstructions is a zero, said apparatus comprising: means for calculating a more significant slice sum, a more significant slice sum+1, and a least significant slice sum of addends of an addition operation in a successive microinstruction; a multiplexer controlled by control signals on a select line, receiving as inputs from said means for calculating the more significant slice sum and the more significant slice sum+1, and having an output connected to an input of said multiplexer; a logic gate with an output connected to said select line for outputting a first control signal when: (i) said least significant slice sum has a carry-out; (ii) first and second successive microinstructions in successive clock cycles are both add operations; and (iii) a destination of the first microinstruction is a source for the addition operation of the second microinstruction; and outputting a second control signal when any of conditions (ii) or (iii) are not met; wherein said multiplexer outputs: the more significant slice sum+1 when the first control signal is outputted; and the more significant slice sum when the second control signal is outputted.

Claim 5

An apparatus for performing an addition operation in a computer on sliced addends in successive microinstructions, the addends having at least a more significant slice and a least significant slice, where a more significant slice in one of the addends in successive microinstructions is a zero, said apparatus comprising: means for calculating a more significant slice sum, a more significant slice sum+1, and a least significant slice sum of addends of an addition operation in a successive microinstruction; a multiplexer controlled by control signals on a select line, receiving as inputs from said means for calculating the more significant slice sum and the more significant slice sum+1, and having an output connected to an input of said multiplexer; a logic gate with an output connected to said select line for outputting a first control signal when: (i) said least significant slice sum has a carry-out; (ii) first and second successive microinstructions in successive clock cycles are both add operations; and (iii) a destination of the first microinstruction is a source for the addition operation of the second microinstruction; and outputting a second control signal when any of conditions (ii) or (iii) are not met; wherein said multiplexer outputs: the more significant slice sum+1 when the first control signal is outputted; and the more significant slice sum when the second control signal is outputted.