US4878191A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiplication circuit capable of operating at a high speed with a small amount of hardware
Assignee: NEC Electronics Corp
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Filing: 1988-02-16
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Granted: 1989-10-31
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Expires: 2008-02-16
Abstract
Abstract A multiplication circuit comprises a zero detector coupled to a multiplier register so as to generate a signal indicative of completion of the multiplication operation when all of predetermined bits of the multiplier register are zero. A right shifter is coupled to the multiplier register so as to shift the input data one bit rightwardly and to put "0" at its most significant bit. The right shifter rewrites the multiplier register with the shifted data having the MSB of "0". Further, a left shifter is coupled to a multiplicand register so as to shift the input data one bit leftwardly and to put "0" at its least significant bit. The left shifter rewrites the multiplicand register with the leftwardly shifted data having the LSB of "0". An adder is coupled to receive a content of a product register and a content of the multiplicand register and to rewrite the product register with the result of an addition between the content of the product register and the content of the multiplicand register when the LSB of the multiplier register is "1".
Inventors
- 👤 Tetsuji Oguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:40
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/527; G06F7/5272
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
309 words
A multiplication circuit comprising: a multiplier register coupled to receive an initial value of a multiplier before start of a multiplication operation; a zero detector coupled to the multiplier register to generate a signal indicative of completion of the multiplication operation when all of predetermined bits of the multiplier register are zero; a first shifter coupled to the multiplier register to receive the bits of the multiplier register so as to shift the input data, one bit in a direction from a more significant bit to a less significant bit, and to put "0" at its most significant bit, the first shifter rewriting the multiplier register with the shifted data having the most significant bit of "0"; a multiplicand register coupled to receive an initial value of a multiplicand before start of a multiplication operation; a second shifter coupled to the multiplicand register to receive the bits of the multiplicand register so as to shift the input data, one bit in a direction from a less significant bit to a more significant bit, and to put "0" at its least significant bit, the second shifter rewriting the multiplicand register with the shifted data having the least significant bit of "0"; a product register coupled to receive an initial value of a product before start of a multiplication operation; and an adder coupled to receive a content of the product register and a content of the multiplicand register and responding to the least significant bit of the multiplier register so as to execute an addition between the content of the product register and the content of the multiplicand register when the least significant bit of the multiplier register is "1", the adder rewriting the product register with the result of the addition, whereby the rewritings of the multiplier register, the multiplicand register and the product register are executed in parallel.
Claim 2
Dependent Claim
309 words
A multiplication circuit comprising: a multiplier register coupled to receive an initial value of a multiplier before start of a multiplication operation; a zero detector coupled to the multiplier register to generate a signal indicative of completion of the multiplication operation when all of predetermined bits of the multiplier register are zero; a first shifter coupled to the multiplier register to receive the bits of the multiplier register so as to shift the input data, one bit in a direction from a more significant bit to a less significant bit, and to put "0" at its most significant bit, the first shifter rewriting the multiplier register with the shifted data having the most significant bit of "0"; a multiplicand register coupled to receive an initial value of a multiplicand before start of a multiplication operation; a second shifter coupled to the multiplicand register to receive the bits of the multiplicand register so as to shift the input data, one bit in a direction from a less significant bit to a more significant bit, and to put "0" at its least significant bit, the second shifter rewriting the multiplicand register with the shifted data having the least significant bit of "0"; a product register coupled to receive an initial value of a product before start of a multiplication operation; and an adder coupled to receive a content of the product register and a content of the multiplicand register and responding to the least significant bit of the multiplier register so as to execute an addition between the content of the product register and the content of the multiplicand register when the least significant bit of the multiplier register is "1", the adder rewriting the product register with the result of the addition, whereby the rewritings of the multiplier register, the multiplicand register and the product register are executed in parallel.
Claim 3
Dependent Claim
58 words
A multiplication circuit as claimed in claim 1 wherein the multiplier register, the zero detector, the first shifter, the multiplicand register, the second shifter, the product register and the adder are connected to receive the same control signal, respectively, so that the respective rewritings of the multiplier register, the multiplicand register and the product register are concurrently executed.
Claim 4
Dependent Claim
94 words
A multiplication circuit as claimed in claim 1 wherein the multiplier register, the zero detector, the first shifter, the multiplicand register, the second shifter, the product register and the adder are connected to receive the same clock signal, respectively, so that the first shifter, the second shifter and the adder receive the respective data at a first half of each clock and output the treated data at a second half of each clock whereby the multiplier register, the multiplicand register and the product register are simultaneously rewritten at a second half of each clock.
Claim 5
Dependent Claim
57 words
A multiplication circuit as claimed in claim 1 further including a data bus coupled to the multiplier register, the multiplicand register and the product register, respectively for supplying the initial values of the multiplier, multiplicand and the product to the multiplier register, the multiplicand register and the product register, respectively, before the start of the multiplication operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-30 | 1993-05-01 | 1993-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-30 | 1997-05-01 | 1997-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-30 | 2001-05-01 | 2001-10-31 | $7700.00 | Window Closed / Lapsed |