US4685077A
Expired / Lapsed
US
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Data processing apparatus having binary multiplication capability
Assignee: CAMBRIDGE PARALLEL PROCESSING Ltd
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Filing: 1985-01-17
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Granted: 1987-08-04
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Expires: 2005-01-17
Abstract
Abstract There is described a data processing apparatus with a binary multiplication capability. The apparatus has an arithmetic and logic unit (ALU) and a operand register. The operand register is divided into two portions, the first of which can be shifted while the second is loaded in parallel. For multiplication, the first portion is used to hold a multiplier and to receive the least significant bits of the result, while the second portion receives the most significant bits of the result. The invention avoids the need for a separate shift register to hold the multiplier. The described apparatus also has a look-ahead facility, for selecting the next bit of the multiplier ahead of its requirement, so that it is immediately available when required.
Inventors
- 👤 Johnson Loo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:08
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/527; G06F7/5272; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3812; G06F2207/382
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
196 words
Data processing apparatus comprising (a) an arithmetic and logic unit (ALU) having first and second inputs, (b) an operand register comprising first and second portions both connected to the first input of the ALU, the first portion being operable as a shift register independently of the operation of the second portion, (c) means for applying a multiplicand to the second input of the ALU, (d) means for loading a multiplier into the first portion of the operand register, (e) means for reading successive bits of the multiplier from said first portion, (f) control means responsive to each multiplier bit read from said first portion, for operating the ALU to produce a partial result equal to the sum of its first and second inputs in the event that the multiplier bit is equal to one, and otherwise equal to the first input, and (g) means for shifting the contents of the first portion one place to the right and inserting the least significant bit of said partial result into the most significant bit position of said first portion, while at the same time loading the remaining bits of said partial result in parallel into said second portion.
Claim 2
Dependent Claim
196 words
Data processing apparatus comprising (a) an arithmetic and logic unit (ALU) having first and second inputs, (b) an operand register comprising first and second portions both connected to the first input of the ALU, the first portion being operable as a shift register independently of the operation of the second portion, (c) means for applying a multiplicand to the second input of the ALU, (d) means for loading a multiplier into the first portion of the operand register, (e) means for reading successive bits of the multiplier from said first portion, (f) control means responsive to each multiplier bit read from said first portion, for operating the ALU to produce a partial result equal to the sum of its first and second inputs in the event that the multiplier bit is equal to one, and otherwise equal to the first input, and (g) means for shifting the contents of the first portion one place to the right and inserting the least significant bit of said partial result into the most significant bit position of said first portion, while at the same time loading the remaining bits of said partial result in parallel into said second portion.
Claim 3
Dependent Claim
31 words
Apparatus according to claim 1 wherein said control means comprises a function register for holding each successive bit of the multiplier, and connected to the ALU to control the opeation thereof.
Claim 4
Dependent Claim
30 words
Apparatus according to claim 1 wherein the first portion of the operand register comprises the more significant half of that register and the second portion comprises the less significant half.
Claim 5
Dependent Claim
215 words
Data processing apparatus comprising (a) an arithmetic and logic unit (ALU) having first and second data inputs and control input, (b) an operand register comprising first and second portions both connected to the first data input of the ALU, the first portion being operable as a shift register independently of the operation of the second portion, (c) means for applying a multiplicand to the second data input of the ALU, (d) means for loading a multiplier into the first portion of the operand register, (e) means for reading a bit from the second-to-last bit position of said first portion, (f) function register means connected to receive said bit read from the first portion, and connected to the control input of the ALU, for operating the ALU to produce a partial result equal to the sum of its first and second data inputs in the event that said bit is equal to one, and otherwise equal to the first data input, and (g) means for shifting the content of the first portion one place to the right and inserting the least significant bit of said partial result into the most significant bit position of said first portion, while at the same time loading the remaining bits of said partial result in parallel into said second portion.
Claim 6
Dependent Claim
215 words
Data processing apparatus comprising (a) an arithmetic and logic unit (ALU) having first and second data inputs and control input, (b) an operand register comprising first and second portions both connected to the first data input of the ALU, the first portion being operable as a shift register independently of the operation of the second portion, (c) means for applying a multiplicand to the second data input of the ALU, (d) means for loading a multiplier into the first portion of the operand register, (e) means for reading a bit from the second-to-last bit position of said first portion, (f) function register means connected to receive said bit read from the first portion, and connected to the control input of the ALU, for operating the ALU to produce a partial result equal to the sum of its first and second data inputs in the event that said bit is equal to one, and otherwise equal to the first data input, and (g) means for shifting the content of the first portion one place to the right and inserting the least significant bit of said partial result into the most significant bit position of said first portion, while at the same time loading the remaining bits of said partial result in parallel into said second portion.
Claim 7
Dependent Claim
63 words
Apparatus according to claim 4 including an input register for holding an input operand, and means operable to transfer the contents of first and second halves of the input register to the first and second portions of the operand register, and alternatively operable to transfer a multiplier from the second half of the input register to the first portion of the operand register.
Claim 8
Dependent Claim
38 words
Apparatus according to claim 5 further including means for transferring the least significant bit of the input register to the function register means simultaneously with the transfer of the contents of the input register to the operand register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-03 | 1991-02-02 | 1991-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-03 | 1995-02-02 | 1995-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-03 | 1999-02-02 | 1999-08-04 | $7700.00 | Window Closed / Lapsed |