US4589086A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing system
Assignee: Siemens AG
•
Filing: 1982-08-30
•
Granted: 1986-05-13
•
Expires: 2002-08-30
Abstract
Abstract A data processing system having an arithmetic unit is designed for a multiplication of n-place numbers in 2's complement according to the Booth algorithm, and for division of unsigned numerals. A 2n-stage shift register is connected over a logical control circuit to the operation code inputs of an ALU. The control circuit automatically forms instruction code signals to the ALU as a function of informational bits derived from the shift register, whereas other operation code input signals are directly connected to the operation code inputs. The control circuit is a sequential circuit having a multiplexer for the selective through-connection of the multiplication code signals, the division code signals, or other operation code signals to the operation code inputs of the ALU.
Inventors
- 👤 Wolfgang Beifuss
- 👤 Bernd Haussmann
- 👤 Michael Pomper
- 👤 Ewald Soutschek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:53
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/535; G06F7/523
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
128 words
In a data processing system having an arithmetic/logical unit, two operand registers with capacity n and a shift register with capacity 2 n designed for a Booth multiplication or division of two operands, the combination comprising; a logical control circuit for supplying operation code inputs to said arithmetic/logical unit, said logical control circuit being connected over a first input to an output of said shift register, a single-place auxiliary register means connecting an input of said logical control circuit to the least significant output of said shift register, said logical control circuit having a multiplexer connected to and responsive to said auxiliary register for the selective connection of operation code signals directly from its inputs and over its outputs to the operation code inputs of said arithmetic/logical unit.
Claim 2
Dependent Claim
128 words
In a data processing system having an arithmetic/logical unit, two operand registers with capacity n and a shift register with capacity 2 n designed for a Booth multiplication or division of two operands, the combination comprising; a logical control circuit for supplying operation code inputs to said arithmetic/logical unit, said logical control circuit being connected over a first input to an output of said shift register, a single-place auxiliary register means connecting an input of said logical control circuit to the least significant output of said shift register, said logical control circuit having a multiplexer connected to and responsive to said auxiliary register for the selective connection of operation code signals directly from its inputs and over its outputs to the operation code inputs of said arithmetic/logical unit.
Claim 3
Dependent Claim
92 words
Apparatus according to claim 1, including a multiplication/division sequence circuit and wherein said multiplexer comprises three groups of switching transistors; means connecting the switching terminals of the switching transistors of said first group to the first input of said multiplication/division sequence circuit, gate means for connecting the switching terminals of the switching transistors of said second group to said first and to a second input of said multiplication/division sequence circuit, and means connecting the switching terminals of the switching transistors of said third group to further inputs of said multiplication/division sequence circuit.
Claim 4
Dependent Claim
36 words
Apparatus according to claim 2, including a gate circuit having two inputs connected to a multiplication signal and to a division signal, and three outputs for the separate selection of the three groups of switching transistors.
Claim 5
Dependent Claim
28 words
Apparatus according to one of the claims 1 through 3, wherein said auxiliary register is connected to said shift register through a gate enabled during a multiplication signal.
Claim 6
Dependent Claim
22 words
Apparatus according to one of the claims 1 through 3, including a plurality of intermediate memories connected to outputs of the multiplexer.
Claim 7
Dependent Claim
18 words
Apparatus according to one of the claims 1 through 3, wherein said auxiliary register comprises a master-slave flip-flop.
Claim 8
Dependent Claim
15 words
Apparatus according to claim 2, including means for connecting clock pulses to said switching transistors.
Claim 9
Dependent Claim
15 words
Apparatus according to claim 5 including means for connecting clock pulses to said intermediate memories.
Claim 10
Dependent Claim
15 words
Apparatus according to claim 6, including means for connecting clock pulses to said master-slave flip-flop.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-12 | 1989-11-11 | 1990-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-12 | 1993-11-11 | 1994-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-12 | 1997-11-11 | 1998-05-13 | $7700.00 | Window Closed / Lapsed |