Multiplication by successive addition with two{40 s complement notation

Claim 2

Serial data bit multiplying apparatus over a time period comprising a frame of words for each multiplication problem wherein a frame includes as many words as there are data bits in a multiplier word comprising, in combination: input first means for supplying a serial data bit multiplier word signal representing a first number wherein the multiplier word signal comprises a plurality of bits ranging from a least significant bit (LSB) to a most significant bit (MSB) wherein the MSB is a sign bit for indicating the polarity of the number represented by the multiplier word; input second means for supplying a serial data bit multiplicand word signal representing a number which also comprises a plurality of bits ranging from an LSB to a MSB with the MSB being a sign bit representing the polarity of the number represented by the multiplicand word; third means, including input means and output means, connected to said first and second means for examining the individual bits in the multiplier word starting with the least significant bit and examining only one bit per word time in the frame and passing the multiplicand word to the output means thereof upon each occurrence of a data bit in the multiplier signal of a first logic value; cumulative adding fourth means connected to the output of said third means for receiving digital words supplied at the output thereof and adding these to a representation of the product obtained in a given frame; output fifth means connected to said fourth means for retrieving the total time shifted data bit cumulatively added product representing the digital product of the multiplier and multiplicand signals at the end of each frame; and sign detection sixth means connected to each of said second means and said fourth means for detecting logic values of signals received therefrom and for forcing the MSB of said representation of the product to be added to the most recently received word from said third means, to said first logic value for Each word time remaining in a given frame after detection of said first logic value in the most significant bit position of both of the signals received from said second and fourth means.

Claim 3

Serial data bit multiplying apparatus over a time period comprising a frame of words for each multiplication problem wherein a frame includes as many words as there are data bits in a multiplier word comprising, in combination: input first means for supplying a serial data bit multiplier word signal representing a first number wherein the multiplier word signal comprises a plurality of bits ranging from a least significant bit (LSB) to a most significant bit (MSB) wherein the MSB is a sign bit for indicating the polarity of the number represented by the multiplier word; input second means for supplying a serial data bit multiplicand word signal representing a number which also comprises a plurality of bits ranging from an LSB to a MSB with the MSB being a sign bit representing the polarity of the number represented by the multiplicand word; third means, including input means and output means, connected to said first and second means for examining the individual bits in the multiplier word starting with the least significant bit and examining only one bit per word time in the frame and passing the multiplicand word to the output means thereof upon each occurrence of a data bit in the multiplier signal of a first logic value, and further including word storage means for a total bit capacity which is one data bit less than the number of data bits in the multiplier word and further storage means, connected to said word storage means, for receiving outputs therefrom and for providing an output representative of the data bit appearing at the output of said first word storage means at the MSB time of each word of the frame for the time duration of the word following the appearance of said data bit at said MSB. cumulative adding fourth means connected to the output of said third means for receiving digital words supplied at the output thereof and adding these to a representation of the product obtained in a given frame; and output fifth means connected to said fourth means for retrieving the total time shifted data bit cumulatively added product representing the digital product of the multiplier and multiplicand signals at the end of each frame.

Claim 4

Serial data bit multiplying apparatus over a time period comprising a frame of words for each multiplication problem wherein a frame includes as many words as there are data bits in a multiplier word comprising, in combination: input first means for supplying a serial data bit multiplier word signal representing a first number wherein the multiplier word signal comprises a plurality of bits ranging from a least significant bit (LSB) to a most significant bit (MSB) wherein the MSB is a sign bit for indicating the polarity of the number represented by the multiplier word; input second means for supplying a serial data bit multiplicand word signal representing a number which also comprises a plurality of bits ranging from an LSB to a MSB with the MSB being a sign bit representing the polarity of the number represented by the multiplicand word; third means, including input means and output means, connected to said first and second means for examining the individual bits in the multiplier word starting with the least significant bit and examining only one bit per word time in the frame and passing the multiplicand word to the output means thereof upon each occurrence of a data bit in the multiplier signal of a first logic value, and further including word storage means for a total bit capacity which is one data bit less than the number of data bits in the multiplier word and further storage means, connected to said word storage means, for receiving outputs therefrom and for providing an output representative of the data bit appearing at the output of said first word storage means at the MSB time of each word of the frame for the time duration of the word following the appearance of said data bit at said MSB. cumulative adding fourth means connected to the output of said third means for receiving digital words supplied at the output thereof and adding these to a representation of the product obtained in a given frame; and output fifth means connected to said fourth means for retrieving the total time shifted data bit cumulatively added product representing the digital product of the multiplier and multiplicand signals at the end of each frame.

Claim 5

Serial data bit multiplying apparatus over a time period comprising a frame of words for each multiplication problem wherein a frame includes as many words as there are data bits in a multiplier word comprising, in combination: input first means for supplying a serial data bit multiplier word signal representing a first number wherein the multiplier word signal comprises a plurality of bits ranging from a least significant bit (LSB) to a most significant bit (MSB) wherein the MSB is a sign bit for indicating the polarity of the number represented by the multiplier word; input second means for supplying a serial data bit multiplicand word signal representing a number which also comprises a plurality of bits ranging from an LSB to a MSB with the MSB being a sign bit representing the polarity of the number represented by the multiplicand word; third means, including input means and output means, connected to said first and second means for examining the individual bits in the multiplier word starting with the least significant bit and examining only one bit per word time in the frame and passing the multiplicand word to the output means thereof upon each occurrence of a data bit in the multiplier signal of a first logic value; cumulative adding fourth means connected to the output of said third means for receiving digital words supplied at the output thereof and adding these to a representation of the product obtained in a given frame, said fourth means comprising word storage means having a capacity equal to one bit less than the multiplicand word, and adding means connected from an output to an input of the word storage means in a feedback manner whereby the word fed back is truncated before being added to any words supplied to said fourth means by said third means; and output fifth means connected to said fourth means for retrieving the total time shifted data bit cumulatively added product representing the digital product of the multiplier and multiplicand signals at the end of each frame.

Claim 6

Serial data bit multiplying apparatus over a time period comprising a frame of words for each multiplication problem wherein a frame includes as many words as there are data bits in a multiplier word comprising, in combination: input first means for supplying a serial data bit multiplier word signal representing a first number wherein the multiplier word signal comprises a plurality of bits ranging from a least significant bit (LSB) to a most significant bit (MSB) wherein the MSB is a sign bit for indicating the polarity of the number represented by the multiplier word; input second means for supplying a serial data bit multiplicand word signal representing a number which also comprises a plurality of bits ranging from an LSB to a MSB with the MSB being a sign bit representing the polarity of the number represented by the multiplicand word; third means, including input means and output means, connected to said first and second means for examining the individual bits in the multiplier word starting with the least significant bit and examining only one bit per word time in the frame and passing the multiplicand word to the output means thereof upon each occurrence of a data bit in the multiplier signal of a first logic value; cumulative adding fourth means connected to the output of said third means for receiving digital words supplied at the output thereof and adding these to a representation of the product obtained in a given frame, said fourth means comprising word storage means having a capacity equal to one bit less than the multiplicand word, and adding means connected from an output to an input of the word storage means in a feedback manner whereby the word fed back is truncated before being added to any words supplied to said fourth means by said third means; and output fifth means connected to said fourth means for retrieving the total time shifted data bit cumulatively added product representing the digital product of the multiplier and multiplicand signals at the end of each frame.

Claim 7

Serial data bit multiplier means comprising, in combination: first signal input means for supplying a serial data bit multiplier word having a given number of bits ranging from an LSB to a MSB wherein the MSB is a sign bit indicating the polarity of the number represented by the multiplier word; second signal input supplying means for supplying a multiplicand serial data bit digital word comprising said given number of bits ranging from an LSB to a MSB with the MSB signifying the polarity of the number represented by the multiplicand word; third signal supplying means for supplying an input word during the first word of a frame of words wherein the number of words in a frame is equal to said given number of data bits in a word; fourth signal supplying means for supplying a logical input signal at the MSB time of each word; first NAND gate means connected to receive said signals from first and third signal supplying means and supplying an output representative thereof; second NAND gate means connected to receive an inverted version of the signal from said fourth signal supplying means and including a further input and an output for supplying signals representative of signals supplied to inputs thereof; third NAND gate means connected to said first and second NAND gate means for receiving output signals therefrom, said third NAND gate means supplying an output signal representative of those signals supplied to the inputs thereof; first word storage means including input means and output means, the input means being connected to said third NAND gate means for receiving the output signal therefrom the storage capacity of said first word storage means being one data bit less than said given number of bits in the multiplier word supplied by said first means; first JK flip-flop means including J, inverted K, and clock input means and true output means; means connecting the output of said first word storage means to the further input of said second NAND gate means, to said J and inverted K inputs of said JK flip-flop means; means supplying the signal from said fourth signal supplying means to the clock input of said JK flip-flop means; first and second AND gate means each including first and second inputs and an output; means connected said true output of said first JK flip-flop means to the first input of each of said first and second AND gate means; means connecting the signal from said third signal supplying means to said second input of said second AND gate means and supplying an inverted version of the signal from said third signal supplying means to said second input of said first AND gate means; multiplying means including a first input connected to said second signal supplying means and further means connected to the outputs of said first and second AND gate means, said multiplying means also including output means, the signal appearing on said output means being identical to that received at said first input means if a given signal is received from said first AND gate means and being a logical inversion thereof plus an LSB of logic 1 if a said given signal is received from said second AND gate means; summing means including a first input connected to the output of said multiplying means, a second input and an output, the output of said summing means representing the additive product of the signals received on first and second inputs; third AND gate means, including first and second inputs connected to Said second signal supplying means and to the output of said summing means for receiving signals therefrom, said third AND gate means also including an inverted third input connected to said third signal supplying means and including an output; second JK flip-flop means including a J input connected to the output of said third AND gate means, a K input connected to said third signal supplying means, a clock input connected to said fourth signal supplying means and a true output; fourth NAND gate means including a first regular input, second and third inverted inputs and an output; second storage means for delaying input signals by one data bit time and including an input connected to said fourth signal supplying means and further including an output connected to said inverted second input of said fourth NAND gate means; means connecting the output of said summing means to said first input of said fourth NAND gate means and connecting the output of said third signal supplying means to said third inverted input of said fourth NAND gate means; fifth NAND gate means including first and second input means and an output means, said first input means of said fifth NAND gate means being connected to said output of said second word storage means and said second input thereof being connected to said true output of said second JK flip-flop means; sixth NAND gate means including first and second inputs connected to the outputs of said fourth and fifth NAND gate means and including an output; third word storage means, having a data bit capacity of one less than said given number of bits in a word, connected between the output of said sixth NAND gate means and said second input of said summing means; and apparatus output means connected to said output of said summing means for supplying a word at the end of each frame of words representative of the product of said multiplier and said multiplicand words supplied by said first and second signal input means.

Claim 8

Serial data bit multiplier means comprising, in combination: first signal input means for supplying a serial data bit multiplier word having a given number of bits ranging from an LSB to a MSB wherein the MSB is a sign bit indicating the polarity of the number represented by the multiplier word; second signal input supplying means for supplying a multiplicand serial data bit digital word comprising said given number of bits ranging from an LSB to a MSB with the MSB signifying the polarity of the number represented by the multiplicand word; third signal supplying means for supplying an input word during the first word of a frame of words wherein the number of words in a frame is equal to said given number of data bits in a word; fourth signal supplying means for supplying a logical input signal at the MSB time of each word; first NAND gate means connected to receive said signals from first and third signal supplying means and supplying an output representative thereof; second NAND gate means connected to receive an inverted version of the signal from said fourth signal supplying means and including a further input and an output for supplying signals representative of signals supplied to inputs thereof; third NAND gate means connected to said first and second NAND gate means for receiving output signals therefrom, said third NAND gate means supplying an output signal representative of those signals supplied to the inputs thereof; first word storage means including input means and output means, the input means being connected to said third NAND gate means for receiving the output signal therefrom the storage capacity of said first word storage means being one data bit less than said given number of bits in the multiplier word supplied by said first means; first JK flip-flop means including J, inverted K, and clock input means and true output means; means connecting the output of said first word storage means to the further input of said second NAND gate means, to said J and inverted K inputs of said JK flip-flop means; means supplying the signal from said fourth signal supplying means to the clock input of said JK flip-flop means; first and second AND gate means each including first and second inputs and an output; means connected said true output of said first JK flip-flop means to the first input of each of said first and second AND gate means; means connecting the signal from said third signal supplying means to said second input of said second AND gate means and supplying an inverted version of the signal from said third signal supplying means to said second input of said first AND gate means; multiplying means including a first input connected to said second signal supplying means and further means connected to the outputs of said first and second AND gate means, said multiplying means also including output means, the signal appearing on said output means being identical to that received at said first input means if a given signal is received from said first AND gate means and being a logical inversion thereof plus an LSB of logic 1 if a said given signal is received from said second AND gate means; summing means including a first input connected to the output of said multiplying means, a second input and an output, the output of said summing means representing the additive product of the signals received on first and second inputs; third AND gate means, including first and second inputs connected to Said second signal supplying means and to the output of said summing means for receiving signals therefrom, said third AND gate means also including an inverted third input connected to said third signal supplying means and including an output; second JK flip-flop means including a J input connected to the output of said third AND gate means, a K input connected to said third signal supplying means, a clock input connected to said fourth signal supplying means and a true output; fourth NAND gate means including a first regular input, second and third inverted inputs and an output; second storage means for delaying input signals by one data bit time and including an input connected to said fourth signal supplying means and further including an output connected to said inverted second input of said fourth NAND gate means; means connecting the output of said summing means to said first input of said fourth NAND gate means and connecting the output of said third signal supplying means to said third inverted input of said fourth NAND gate means; fifth NAND gate means including first and second input means and an output means, said first input means of said fifth NAND gate means being connected to said output of said second word storage means and said second input thereof being connected to said true output of said second JK flip-flop means; sixth NAND gate means including first and second inputs connected to the outputs of said fourth and fifth NAND gate means and including an output; third word storage means, having a data bit capacity of one less than said given number of bits in a word, connected between the output of said sixth NAND gate means and said second input of said summing means; and apparatus output means connected to said output of said summing means for supplying a word at the end of each frame of words representative of the product of said multiplier and said multiplicand words supplied by said first and second signal input means.