ECL circuit having an improved emitter follower output circuit

Claim 2

A semiconductor integrated circuit having an emitter follower circuit coupled with an output of a logic circuit, comprising: a first emitter follower means for receiving an output signal of a logic circuit, an output signal obtained at an emitter output of the first emitter follower means forming a finalized output signal of the logic circuit; second emitter follower means for receiving the output signal of the logic circuit, said first and second emitter follower means being supplied with the same output signal of the same phase derived from said logic circuit; detecting means, connected to said first and second emitter follower means, for detecting a difference in level between the output signal of the first emitter follower means and an output signal of the second emitter follower means; and driving means, connected to said detection means, for driving a load capacitance, coupled with the emitter output of the first emitter follower means, during a period when the detecting means detects the difference.

Claim 3

A semiconductor integrated circuit having an emitter follower circuit coupled with an output of a logic circuit, comprising: a first emitter follower means for receiving an output signal of a logic circuit, an output signal obtained at an emitter output of the first emitter follower means forming a finalized output signal of the logic circuit; second emitter follower means for receiving the output signal of the logic circuit, said first and second emitter follower means being supplied with the same output signal of the same phase derived from said logic circuit; detecting means, connected to said first and second emitter follower means, for detecting a difference in level between the output signal of the first emitter follower means and an output signal of the second emitter follower means; first driving means, connected to said emitter output of said first emitter follower means, for driving a load capacitance, coupled with the emitter output of the first emitter follower means, during a period when the detecting means detects the difference; and second driving means, connected to said detecting means and said first driving means, for driving the first driving means in response to the difference detected by the detecting means.

Claim 4

A semiconductor integrated circuit having an emitter follower circuit coupled with an output of a logic circuit, comprising: a first emitter follower means for receiving an output signal of a logic circuit, an output signal obtained at an emitter output of the first emitter follower means forming a finalized output signal of the logic circuit; second emitter follower means for receiving the output signal of the logic circuit, said first and second emitter follower means being supplied with the same output signal of the same phase derived from said logic circuit; detecting means, connected to said first and second emitter follower means, for detecting a difference in level between the output signal of the first emitter follower means and an output signal of the second emitter follower means; first driving means, connected to said emitter output of said first emitter follower means, for driving a load capacitance, coupled with the emitter output of the first emitter follower means, during a period when the detecting means detects the difference; and second driving means, connected to said detecting means and said first driving means, for driving the first driving means in response to the difference detected by the detecting means.

Claim 5

A semiconductor integrated circuit as claimed in claim 2, wherein the first emitter follower means comprises an npn-type transistor, a base terminal of which is supplied with the output signal of the logic circuit, and an emitter terminal thereof is connected to the detecting means, and wherein the second emitter follower means comprises an npn-type transistor, a base terminal of which is supplied with the output signal of the logic circuit, and an emitter terminal thereof is connected to the detecting means.

Claim 6

A semiconductor integrated circuit as claimed in claim 2, wherein the detecting means comprises a differential amplifier.

Claim 7

A semiconductor integrated circuit as claimed in claim 4, wherein the differential amplifier comprises a first npn-type transistor and a second npn-type transistor, and wherein a base terminal of the first transistor receives the output signal of the first emitter follower means, and a base terminal of the second transistor receives the output signal of the second emitter follower means, and wherein emitter terminals of the first and second transistors are supplied with a constant current supply source, a collector terminal of the first transistor is connected to the output of the first emitter follower means, and a collecter terminal of the second transistor is connected to a positive power supply source.

Claim 8

A semiconductor integrated circuit as claimed in claim 2, wherein the second driving means comprises an npn-type transistor and a resistor, a base terminal of which is connected to an output of the detecting means, and wherein an emitter terminal of the transistor is connected to the first driving means, and a collector terminal thereof is connected to a positive power supply source and to the base terminal through the resistor.

Claim 9

A semiconductor integrated circuit as claimed in claim 6, wherein the second driving means further comprises a level shift diode, an anode terminal of which is connected to the emitter terminal of the transistor of the second driving means, and a cathode terminal thereof is connected to an input of the first driving means.

Claim 10

A semiconductor integrated circuit as claimed in claim 2, wherein the first driving means comprises an npn-type transistor and two resistors, a base terminal of which is connected to an output of the second driving means, and wherein a collector terminal thereof is connected to the output of the first emitter follower means, and base and emitter terminals thereof are connected to a negative power supply source through the respective resistors.

Claim 11

A semiconductor integrated circuit as claimed in claim 3, wherein the differential amplifier comprises a first npn-type transistor and a second npn-type transistor, and wherein a base terminal of the first transistor receives the output signal of the first emitter follower means, and a base terminal of the second transistor receives the output signal of the second emitter follower means, and wherein emitter terminals of the first and second transistors are supplied with a constant current supply source, a collector terminal of the first transistor is connected to the output of the first emitter follower means, and a collector terminal of the second transistor is connected to a positive power supply source through a resistor, and wherein the second driving means comprises an npn-type transistor and a level shift diode, a base terminal of which is connected to the collector terminal of the second transistor of the detecting means, and wherein an emitter terminal of the transistor of the second driving means is connected to the first driving means through the level shift diode, and a collector terminal of the transistor of the second driving means is connected to a positive power supply source and to the base terminal through the resistor.

Claim 12

A semiconductor integrated circuit as claimed in claim 2, wherein the second driving means comprises a pnp-type transistor and a resistor, a base terminal of which is connected to an output of the detecting means, and wherein a collector terminal thereof is connected directly to the first driving means, and an emitter terminal thereof is connected to a positive power supply source and also to the base terminal thereof through the resistor.

Claim 13

A semiconductor integrated circuit as claimed in claim 4, wherein a differential amplifier comprises a first npn-type transistor and a second npn-type transistor, and wherein a base terminal of the first transistor receives the output signal of the first emitter follower means, and a base terminal of the second transistor receives the output signal of the second emitter follower means, and wherein emitter terminals of the first and second transistors are supplied with a constant current supply source, a collector terminal of the first transistor is connected to the output of the first emitter follower means, and a collector terminal of the second transistor is connected to a positive power supply source, and wherein the second driving means comprises a pnp-type transistor and a resistor, a base terminal of which is connected to an output of the first transistor of the detecting means, and wherein a collector terminal thereof is connected directly to the first driving means, and an emitter terminal thereof is connected to a positive power supply source and also to the base terminal thereof through the resistor.

Claim 14

A semiconductor integrated circuit as claimed in claim 2, wherein the logic circuit is an emitter coupled logic circuit.