Patent US4877752A successfully refreshed from Google Patents.
US4877752A
Expired / Lapsed
US
⏱️ 0.0 years remaining
3-D packaging of focal plane assemblies
Assignee: United States Department of the Army
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Filing: 1988-10-31
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Granted: 1989-10-31
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Expires: 2008-10-31
Abstract
Abstract In three-dimensional packaging of focal plane signal processing electroni the necessity of routing conductors from the face of the die to the edge of the die in the module for placement of inter-connection pads for interconnection to the next assembly presents the problem of electrical isolation of the conductors from adjacent silicon dies and their underlying silicon substrate. This problem is avoided by the use of a gold ribbon lead that is bonded to the face of each die. The ribbons function as electrically isolated conductive risers upon which inter-connection pads are placed for connection to the next assembly and as precision spacers between stacked dies during module assembly.
Inventors
- 👤 William L. Robinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:46
CPC Classifications
H; H10; H10W; H10W90/00; H10W72/00; H10W72/834; H10W90/20; H10W90/26; Y; Y10; Y10S; Y10S148/00; Y10S148/164
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
246 words
A method for three-dimensional packaging of a focal plane module assembly, comprising the steps of: processing a silicon wafer in the customary manner to make electronic dies having dielectric material on a surface; cutting said wafer into multiple individual dies, said dies each having a front side and a back side and further having said dielectric material on said back side; bonding a gold ribbon to said front side of each die, using a suitable micro-joining process, said ribbon having a first end and a second end, so that said first end is attached to said front side of said die away from edges of said die and said second end extends over an edge of said die to form a gold ribbon extension of a suitable length; stacking and aligning said dies in an alignment mode and compressing said dies together to a preset total thickness to produce a module, said module having a top surface and a bottom surface, said top and bottom surfaces containing said gold ribbon extensions; back filling spaces between individual dies with epoxy and curing; depositing and curing dielectric insulation material to a suitable thickness on said top surface of said module; removing any excess of said gold ribbon extensions and polishing said dielectric insulation material on said top surface; resisting said top surface and exposing tips of said gold ribbons; depositing conductive bond pads so that said bond pads are in contact with said tips of said gold ribbons.
Claim 2
Independent Claim
246 words
A method for three-dimensional packaging of a focal plane module assembly, comprising the steps of: processing a silicon wafer in the customary manner to make electronic dies having dielectric material on a surface; cutting said wafer into multiple individual dies, said dies each having a front side and a back side and further having said dielectric material on said back side; bonding a gold ribbon to said front side of each die, using a suitable micro-joining process, said ribbon having a first end and a second end, so that said first end is attached to said front side of said die away from edges of said die and said second end extends over an edge of said die to form a gold ribbon extension of a suitable length; stacking and aligning said dies in an alignment mode and compressing said dies together to a preset total thickness to produce a module, said module having a top surface and a bottom surface, said top and bottom surfaces containing said gold ribbon extensions; back filling spaces between individual dies with epoxy and curing; depositing and curing dielectric insulation material to a suitable thickness on said top surface of said module; removing any excess of said gold ribbon extensions and polishing said dielectric insulation material on said top surface; resisting said top surface and exposing tips of said gold ribbons; depositing conductive bond pads so that said bond pads are in contact with said tips of said gold ribbons.
Claim 3
Dependent Claim
22 words
A method as cited in claim 1, further including said gold ribbons each being approximately 0.003 inches wide and 0.0005 inches thick.
Claim 4
Dependent Claim
23 words
A method as cited in claim 2, further including extending said gold ribbons over said edge of said die by approximately 0.010 inches.
Claim 5
Dependent Claim
23 words
A method as cited in claim 3, including lapping said back surface of said wafer to a desired thickness less approximately 0.0005 inches.
Claim 6
Dependent Claim
113 words
In a method of three-dimensional packaging of focal plane assemblies wherein silicon dies are stacked together vertically with insulation therebetween and bonded to form a module, said dies having a front and back surface and said module having a top surface and a bottom surface, the improvement comprising: bonding a gold ribbon having a first end and a second end on each die front surface at said first end and said second end extending above said top and bottom surface of said module, said gold ribbon functioning as an electrically insulated conductive riser on which an inter-connection pad may be deposited and as a precision spacer between said silicon dies within said module.
Claim 7
Dependent Claim
113 words
In a method of three-dimensional packaging of focal plane assemblies wherein silicon dies are stacked together vertically with insulation therebetween and bonded to form a module, said dies having a front and back surface and said module having a top surface and a bottom surface, the improvement comprising: bonding a gold ribbon having a first end and a second end on each die front surface at said first end and said second end extending above said top and bottom surface of said module, said gold ribbon functioning as an electrically insulated conductive riser on which an inter-connection pad may be deposited and as a precision spacer between said silicon dies within said module.
References Cited (Backward Citations)
US4734380A
Cited
US4737470A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-30 | 1993-05-01 | 1993-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-30 | 1997-05-01 | 1997-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-30 | 2001-05-01 | 2001-10-31 | $7700.00 | Window Closed / Lapsed |