Logic integrated circuit for scan path system

Claim 1

A logic integrated circuit for performing scan path testing of a combination circuit having a plurality of outputs, comprising: a plurality of flipflops coupled in a cascaded arrangement, each of said flipflops having a data input, a data output and a clock input; a clock terminal commonly connected to the clock inputs of all the plurality of flipflops; a scan input terminal connected to the data input of a first flipflop of said flipflops; a scan output terminal connected to the data output of a last flipflop of said flipflops; a plurality of selectors each located just before each of the flipflops, each of the selectors except a first selector having a first input connected to the data output of an immediately preceding flipflop, each of said selectors having a second input connected to a corresponding one of the outputs of the combination circuit, an output connected to the data input of an immediately succeeding flipflop and a selection control input; and a counter having an input connected to the clock terminal and an output connected to the selection control input of each selector, the counter generating a frequency division signal having a frequency division ratio equivalent to the number of the flipflops, so that when the counter does not generate a frequency division signal, selectors supply the data output of an immediately preceding flipflop to the data input of the immediately succeeding flipflop whereby a shift register is formed by all the flipflops, and when the counter generates the frequency division signal, selectors supply the corresponding output of the combination circuit to the data input of the immediately succeeding flipflop whereby the flipflops do not form the shift register and function to latch the corresponding outputs of the combination circuit.