US4581740A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transfer circuit for defect inspection of an integrated circuit
Assignee: Toshiba Corp
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Filing: 1983-12-22
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Granted: 1986-04-08
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Expires: 2003-12-22
Abstract
Abstract A logic circuit is formed on a gate array chip together with a custom-circuit. Bonding pads mounted on the gate array chip are used as the terminals which send forth or receive data and control signals. The logic circuit is provided with a shift register for holding data to test the flip-flops of the custom-circuit and output data from the flip-flops. The shift register comprises the stages each of which holds 1-bit data selected by a read control signal. The output terminals of the stages are respectively connected to the input terminals of the flip-flops of the custom-circuit through the AND gates which are rendered conducting in response to a set control signal. The output terminals of the flip-flops are connected to the input terminals of the respective stages of the shift register.
Inventors
- 👤 Tsuneo Kinoshita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:51
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541; G01R31/318516
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
130 words
A transfer circuit for defect inspection of an integrated circuit comprising: first and second control terminals for receiving a control signal and an enable signal, respectively; trapping means including a plurality of flip-flops which are interposed in said integrated circuit to trap intermediate data being generated therein and act as part of said integrated circuit; shift register means, coupled to said first control terminal, and having both series and parallel input ports for receiving test data and the output data of said plural flip-flops, respectively, and selectively holding one of said test and output data in accordance with the control signal; and preset means, coupled to said second control terminal, for setting the contents of said shift register means in said plurality of flip-flops in response to the enable signal.
Claim 2
Dependent Claim
130 words
A transfer circuit for defect inspection of an integrated circuit comprising: first and second control terminals for receiving a control signal and an enable signal, respectively; trapping means including a plurality of flip-flops which are interposed in said integrated circuit to trap intermediate data being generated therein and act as part of said integrated circuit; shift register means, coupled to said first control terminal, and having both series and parallel input ports for receiving test data and the output data of said plural flip-flops, respectively, and selectively holding one of said test and output data in accordance with the control signal; and preset means, coupled to said second control terminal, for setting the contents of said shift register means in said plurality of flip-flops in response to the enable signal.
Claim 3
Dependent Claim
26 words
A transfer circuit according to claim 1, wherein said shift register means comprises a plurality of cascade arranged registers, each of which holds one-bit of data.
Claim 4
Dependent Claim
13 words
A transfer circuit according to claim 2, wherein said registers are D-type flip-flops.
Claim 5
Dependent Claim
38 words
A transfer circuit according to claim 2, wherein said preset means comprises a plurality of first gate circuits which respond to the enable signal and deliver data held by said registers to respective flip-flops of said trapping means.
Claim 6
Dependent Claim
111 words
A transfer circuit according to claim 4, wherein said first gate circuit includes a first AND gate having a first input terminal connected to an output terminal of said registers, a second input terminal connected to said second control terminal, and an output terminal connected to an input terminal of the flip-flops in said trapping means through an OR gate; and a second AND gate having a first input terminal to receive the intermediate data, a second input terminal to be supplied with the enable signal through an inverter, and an output terminal connected to one of the input terminals of said flip-flops in said trapping means through said OR gate.
Claim 7
Dependent Claim
49 words
A transfer circuit according to claim 2, wherein said shift register means comprises a plurality of second gate circuits which respectively provide output data of the flip-flops in said transfer means to said registers of said shift register means in response to the control signal at a first level.
Claim 8
Dependent Claim
64 words
A transfer circuit according to claim 6, wherein said second gate circuit is an AND gate having a first input terminal connected to one of the output terminals of the flip-flops in said trapping means, a second input terminal connected to the first control terminal, and an output terminal connected to one of the input terminals of the registers in said shift register means.
Claim 9
Dependent Claim
102 words
A transfer circuit according to claim 6, wherein said second gate circuit includes a first AND gate having a first input terminal supplied with one-bit data to be shifted, a second input terminal to receive the control signal through an inverter, and an output terminal connected to one of the registers in said shift register means through an OR gate; and, a second AND gate having a first input terminal supplied with output data from one of the flip-flops in said trapping means, and an output terminal connected to one of the registers in said shift register means through said OR gate.
Claim 10
Dependent Claim
29 words
A transfer circuit according to claim 1, wherein said trapping means further includes a third control terminal to which a second enable signal for resetting the flip-flops is supplied.
Claim 11
Dependent Claim
49 words
A transfer circuit according to claim 2, further comprising a third control terminal for receiving a second enable signal; and a gate circuit which responds to the second enable signal and feeds output data of the last register of said shift register means back to the initial register thereof.
Claim 12
Dependent Claim
20 words
A transfer circuit according to claim 1, which is formed on a gate array chip together with said integrated circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-07 | 1989-10-07 | 1990-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-07 | 1993-10-07 | 1994-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-07 | 1997-10-07 | 1998-04-08 | $7700.00 | Window Closed / Lapsed |