Patent US2705447A successfully refreshed from Google Patents.
Patent US4876639A successfully refreshed from Google Patents.
US4876639A
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Method and circuitry for causing sixteen bit microprocessor to execute eight bit op codes to produce either internal sixteen bit operation or internal eight bit operation in accordance with an emulation bit
Assignee: Individual
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Filing: 1988-04-06
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Granted: 1989-10-24
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Expires: 2008-04-06
Abstract
Abstract A sixteen bit microprocessor includes an emulation bit that is loaded into an instruction register with 8 bit op codes. If the emulation bit is a "1", the 16 bit microprocessor operates internally as a 6502 type eight bit microprocessor, thereby emulating a 6502 microprocessor. If the emulation bit is set to a "0", the 16 bit microprocessor executes an instruction set of which the 6502 instruction set is a subset to effectuate internal 16 bit operation.
Inventors
- 👤 William D. Mensch, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:12
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/3017; G06F9/30174; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7832; G06F9/30181; G06F9/30185
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
269 words
A method of operating a 2 N bit microprocessor comprising the steps of: (a) setting an emulation bit in a status register in the 2 N bit microprocessor to a first logical level; (b) setting levels of a memory width bit and a register width bit in the status register to first logic levels in response to the first logic level of said emulation bit; (c) loading a 2 N-M bit op code in an instruction register, said op code being one of a set of 2 N-M bit op codes that includes all of the op codes of a different 2 N-M bit microprocessor, and also loading the emulation bit into the instruction register; (d) decoding the 2 N-M bit op code and the emulation bit in the instruction register to produce a first group of transfer signals that are useful for effectuating 2 N bit information transfers between various registers and buses of said 2 N bit microprocessor; and (e) further decoding certain ones of said first group transfer signals and said memory width bit and said register width bit to produce a second group of transfer signals that are useful in effectuating 2 N-M bit information transfers between various buses and registers and arithmetic logic units of said 2 N bit microprocessor, said first and second groups of transfer signals causing said 2 N bit microprocessor to emulate said 2 N-M bit microprocessor when said emulation bit has said first level by executing a same set of instructions as said 2 N-M bit microprocessor, wherein N and M are integers and N is greater than M.
Claim 2
Independent Claim
269 words
A method of operating a 2 N bit microprocessor comprising the steps of: (a) setting an emulation bit in a status register in the 2 N bit microprocessor to a first logical level; (b) setting levels of a memory width bit and a register width bit in the status register to first logic levels in response to the first logic level of said emulation bit; (c) loading a 2 N-M bit op code in an instruction register, said op code being one of a set of 2 N-M bit op codes that includes all of the op codes of a different 2 N-M bit microprocessor, and also loading the emulation bit into the instruction register; (d) decoding the 2 N-M bit op code and the emulation bit in the instruction register to produce a first group of transfer signals that are useful for effectuating 2 N bit information transfers between various registers and buses of said 2 N bit microprocessor; and (e) further decoding certain ones of said first group transfer signals and said memory width bit and said register width bit to produce a second group of transfer signals that are useful in effectuating 2 N-M bit information transfers between various buses and registers and arithmetic logic units of said 2 N bit microprocessor, said first and second groups of transfer signals causing said 2 N bit microprocessor to emulate said 2 N-M bit microprocessor when said emulation bit has said first level by executing a same set of instructions as said 2 N-M bit microprocessor, wherein N and M are integers and N is greater than M.
Claim 3
Dependent Claim
114 words
The method of claim 1 including the steps of: i. setting said emulation bit to a second logic level; ii. setting said memory width bit and said register width bits to second logic levels; iii. repeating steps (c) and (d); iv. further decoding certain ones of said first group of transfer signals and said memory width bit and said register width bit to produce said second group of transfer signals such that said second group of transfer signals are useful in effectuating 2 N bit information transfers between said various buses and registers and arithmetic logic units of said chip to effectuate full 2 N bit internal operation of said 2 N bit microprocessor.
Claim 4
Dependent Claim
26 words
The method of claim 2 wherein said 2 N-M bit op code is one not included in the instruction set of said 2 N-M bit microprocessor.
Claim 5
Dependent Claim
42 words
The method of claim 2 wherein said 2 N-M bit op code is one not included in the instruction set of said 2 N bit microprocessor when said 2 N bit microprocessor is operating to effectuate full 2 N bit internal operation.
Claim 6
Dependent Claim
17 words
The method of claim 2 wherein N is equal to 4 and M is equal to 1.
Claim 7
Dependent Claim
277 words
A 2 N bit microprocessor comprising in combination: (a) a status register; (b) means for setting an emulation bit in the status register to a first logical level; (c) means for setting a memory width bit and a register width bit in the status register to a first logic level in response to the first logic level of said emulation bit; (d) an instruction register; (e) means for loading a 2 N-M bit op code in the instruction register, said op code being one of a set of 2 N-M bit op codes that includes all of the op codes of a different 2 N-M bit microprocessor, and also loading the emulation bit into the instruction register; (f) means for decoding the 2 N-N bit op code and the emulation bit in the instruction register to produce a first group of transfer signals that are useful for effectuating 2 N-M bit information transfers between various registers and buses of said 2 N bit microprocessor; and (g) means for further decoding certain ones of said first group of transfer signals and said memory width bit and said register width bit to produce a second group of transfer signals that are useful in effectuating 2 N-M bit information transfers between various buses and registers and arithmetic logic units of said 2 N bit microprocessor, said first and second groups of transfer signals causing said 2 N bit microprocessor to emulate said 2 N-M bit microprocessor when said emulation bit has its first logic level by executing a same set of instructions as said 2 N-M bit microprocessor, wherein N and M are integers and N is greater than M.
Claim 8
Dependent Claim
277 words
A 2 N bit microprocessor comprising in combination: (a) a status register; (b) means for setting an emulation bit in the status register to a first logical level; (c) means for setting a memory width bit and a register width bit in the status register to a first logic level in response to the first logic level of said emulation bit; (d) an instruction register; (e) means for loading a 2 N-M bit op code in the instruction register, said op code being one of a set of 2 N-M bit op codes that includes all of the op codes of a different 2 N-M bit microprocessor, and also loading the emulation bit into the instruction register; (f) means for decoding the 2 N-N bit op code and the emulation bit in the instruction register to produce a first group of transfer signals that are useful for effectuating 2 N-M bit information transfers between various registers and buses of said 2 N bit microprocessor; and (g) means for further decoding certain ones of said first group of transfer signals and said memory width bit and said register width bit to produce a second group of transfer signals that are useful in effectuating 2 N-M bit information transfers between various buses and registers and arithmetic logic units of said 2 N bit microprocessor, said first and second groups of transfer signals causing said 2 N bit microprocessor to emulate said 2 N-M bit microprocessor when said emulation bit has its first logic level by executing a same set of instructions as said 2 N-M bit microprocessor, wherein N and M are integers and N is greater than M.
Claim 9
Dependent Claim
114 words
The 2 N bit microprocessor of claim 6 including: i. means for setting said emulation bit to a second logic level; ii. means for setting said memory width bit and said register width bits to second logic levels; iii. means for further decoding certain ones of said first group of transfer signals and said memory width bit and said register width bit to produce said second group of transfer signals such that said second group of transfer signals is useful in effectuating 2 N bit information transfers between said various buses and registers and arithmetic logic units of said chip to effectuate full 2 N bit internal operation of said 2 N bit microprocessor.
Claim 10
Dependent Claim
29 words
The 2 N bit microprocessor of claim 7 wherein said 2 N-M bit op code is one not included in the instruction set of said 2 N-M bit microprocessor.
Claim 11
Dependent Claim
35 words
The 2 N bit microprocessor of claim 7 wherein said 2 N-M bit op code is one not included in the instruction set of said 2 N to effectuate full 2 N bit internal operation.
Claim 12
Dependent Claim
20 words
The 2 N bit microprocessor of claim 7 wherein N is equal to 4 and M is equal to 1.
References Cited (Backward Citations)
US4084235A
Cited
US4236204A
Cited
US4415969A
Cited
US4403284A
Cited
US4618925A
Cited
US4654789A
Cited
US4677548A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-23 | 1993-04-24 | 1993-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-23 | 1997-04-24 | 1997-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-23 | 2001-04-24 | 2001-10-24 | $7700.00 | Window Closed / Lapsed |