Oversampling A/D converter comprising an additional capacitor switched in synchronism with switchin of an input capacitor

Claim 2

In an oversampling analog-to-digital converter having a converter input terminal supplied with an input analog signal, and comprising an input switched capacitor connected to said input terminal for sampling said analog signal into output electric charges, an integrator for integrating input electric charges into an integrated signal, a quantizer for quantizing said integrated signal into an output digital signal, a control logic responsive to said digital signal for producing a predetermined number of control signals, a reference voltage source, a capacitor array coupled to said reference voltage source and responsive to said control signals for producing controlled electric charges, and combining means connected to said input switched capacitor, said capacitor array, and said integrator for combining said output electric charges and said controlled electric charges into said input electric charges, the improvement wherein said combining means comprises: an additional switched capacitor connected to said capacitor array for sampling in cooperation with said capacitor array said controlled electric charges into additional electric charges in synchronism with sampling of said analog signal; and summing means connected to said input switched capacitor, said additional switched capacitor, and said integrator for summing said output electric charges and said additional electric charges into said input electric charges.

Claim 3

An oversampling analog-to-digital converter as claimed in claim 1, said input switched capacitor comprising an input capacitor coupled to said converter input terminal, having a first capacitance, and switched to produce said output electric charges, said integrator comprising an operational amplifier having a positive input terminal grounded, a negative input terminal, and an amplifier output terminal for said integrated signal, said capacitor array comprising a common signal line, a reference capacitor having a reference capacitance, and weighted capacitors having weighted capacitances equal to 2 k times said reference capacitance, respectively, where k represents natural numbers starting at unity and ending at said predetermined number less one, said reference capacitor and said weighted capacitors being connected to said common signal line and coupled to said reference voltage source to be controlled by the respective control signals and to collectively produce said controlled electric charges, wherein: said integrator comprising an integrating capacitor connected between said negative input terminal and said amplifier output terminal and having a second capacitance; said additional switched capacitor comprising an additional capacitor connected to said common signal line, having a third capacitance, and switched in synchronism with switching of said input capacitor to produce said additional electric charges in cooperation with said reference and said weighted capacitors; said summing means being for connecting a combination of said input capacitor and said additional capacitor to said negative input terminal in synchronism with switching of said input capacitor; each of said first through said third capacitances being substantially equal to said reference capacitance.

Claim 4

An oversampling analog-to-digital converter as claimed in claim 2, said input switched capacitor comprising an input switch for connecting said input capacitor to said converter input terminal and to ground successively in each oversampling period, said reference capacitor and said weighted capacitors being coupled to said reference voltage source through a switch array for connecting selected ones of said reference and said weighted capacitors and all of said reference and said weighted capacitors to said reference voltage source when said input switch connects said input capacitor to said converter input terminal and to ground, respectively, said selected ones of the reference and the weighted capacitors being selected in response to said control signals, wherein: said additional switched capacitor comprising an additional switch for disconnecting and connecting said additional capacitor to ground when said input switch connects said input capacitor to said converter input terminal and to ground, respectively; said summing means comprising a connecting switch for connecting said combination to said negative input terminal and to ground when said input switch connects said input capacitor to said converter input terminal and to ground, respectively.