US4736188A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog to digital converters
Assignee: Microchip Technology Caldicot Ltd
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Filing: 1986-02-21
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Granted: 1988-04-05
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Expires: 2006-02-21
Abstract
Abstract A high resolution analog to digital converter comprising a low resolution analog to digital converter and an interpolating digital to analog converter, the interpolating digital to analog converter having a second order digital controller and a one bit quantiser arranged in a feedback loop. The low resolution analog to digital converter is coupled to a multi-stage decimation filter having an algorithm of any stage thereof determined in dependence upon the algorithm of the immediately preceding stage.
Inventors
- 👤 Thomas Jackson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:37
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/30; H03M3/39; H03M3/412; H03M3/422; H03M3/424; H03M3/428
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
155 words
A high resolution analogue to digital converter comprising combiner means for receiving an analogue input signal, an analogue controller means for receiving an output from the combiner means, a low resolution analogue to digital converter for receiving an output from the analogue controller means, and an interpolating digital to analogue converter arranged in a feedback loop to the combiner means, the interpolating digital to analogue converter comprising a further combiner means for receiving a digital input, digital controller means for receiving an output from the further combiner means, digital slicer means for receiving an output from the digital controller means and feedback means for affording the output of the digital slicer means to the further combiner means, a multi-stage decimation filter coupled to the output of the low resolution analogue to digital converter, the multistage decimation filter having the algorithm of any stage thereof determined in dependence upon the algorithm of the immediately preceding stage.
Claim 2
Dependent Claim
155 words
A high resolution analogue to digital converter comprising combiner means for receiving an analogue input signal, an analogue controller means for receiving an output from the combiner means, a low resolution analogue to digital converter for receiving an output from the analogue controller means, and an interpolating digital to analogue converter arranged in a feedback loop to the combiner means, the interpolating digital to analogue converter comprising a further combiner means for receiving a digital input, digital controller means for receiving an output from the further combiner means, digital slicer means for receiving an output from the digital controller means and feedback means for affording the output of the digital slicer means to the further combiner means, a multi-stage decimation filter coupled to the output of the low resolution analogue to digital converter, the multistage decimation filter having the algorithm of any stage thereof determined in dependence upon the algorithm of the immediately preceding stage.
Claim 3
Dependent Claim
83 words
A high resolution analogue to digital converter as claimed in claim 1 wherein the digital controller comprises summing means, first delay means connected to the summing means, second delay means connected to the first delay means, further summing means connected to the second delay means, a feedback loop for affording the output of the further summing means to the summing means, and a feed forward loop, including multiplier means, for affording an output from the first delay means to the further summing means.
Claim 4
Dependent Claim
52 words
A high resolution analogue to digital converter as claimed in claim 1 wherein the digital to analogue converter provides a bit stream having a mark to space ratio proportional to the output word from the low resolution analogue to digital converter, which bit stream is subtractively combined with the analogue input signal.
Claim 5
Dependent Claim
63 words
A high resolution analogue to digital converter as claimed in claim 1 wherein the digital to analogue converter provides a bit stream having a mark to space ratio proportional to the output word from the low resolution analogue to digital converter, which bit stream is passed via an inverter to the combiner means where it is additively combined with the analogue input signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-05 | 1991-10-05 | 1992-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-05 | 1995-10-05 | 1996-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-05 | 1999-10-05 | 2000-04-05 | $7700.00 | Window Closed / Lapsed |