Memory device with integrated error detection and correction

Claim 1

A semiconductor memory device comprising: a first memory array having stored therein a plurality of data words each comprising a predetermined number of information bits; an integrated error detection and correction circuit including a second memory array having stored therein a plurality of bits generated in accordance with a predefined error detect/correct code, the second memory array being programmable to create error detection and correction data on the basis of which bits in error in said first memory array are to be detected and corrected, information detecting circuitry associated with said first memory array to detect information bits red from said first memory array, the information detecting circuitry comprising a plurality of information detecting units, said plurality being equal in number to the predetermined number of information bits, error detecting circuitry associated with said second memory array to detect each error bit read from said first memory array and provided by said information detecting circuitry, the error detecting circuitry comprising a plurality of error detection and correction data detecting units, the plurality of error detection and correction data detecting units being equal in number to said plurality of information detecting units and each unit being operative to produce an error signal in response to an erroneous information bit read from said first memory array through said information detecting circuitry, and an error correction circuit operatively intervening between said information detecting circuitry and said error detection and correction data detecting units to invert the logic state of each erroneous information bit read from said first memory array through said information detecting circuitry.