Patent US4875210A successfully refreshed from Google Patents.
US4875210A
Expired / Lapsed
US
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Automatic circuit tester control system
Assignee: Teradyne Inc
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Filing: 1988-01-06
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Granted: 1989-10-17
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Expires: 2008-01-06
Abstract
Abstract Apparatus for providing high speed control of digital test patterns in automatic test equipment, the apparatus including a data random access memory (RAM) storing data of nonsequential vectors, a sequential data memory storing blocks of data of sequential vectors, the sequential data memory having higher capacity than the data RAM, a formatter for receiving data from the data RAM or the sequential data memory and using it to provide inputs to a circuit under test, and a sequence controller controlling selective routing of data from the data RAM or the sequential data memory to the formatter.
Inventors
- 👤 John L. Russo
- 👤 Robert H. Van der Kloot
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:51
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31919; G01R31/31921; G01R31/31928
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
169 words
Apparatus for providing high speed control of digital test patterns in automatic test equipment, said apparatus comprising, a first memory circuit including a data random access memory (RAM) storing data of nonsequential vectors, said data RAM having a first storage capacity, a second memory circuit including a sequential data memory storing blocks of data of sequential vectors, said sequential memory having more storage capacity than said first storage capacity, a formatter for receiving data from said data RAM or said sequential data memory and using the data to provide inputs to a circuit under test, a sequence controller controlling said first and second memory circuits for selectively routing data from said data RAM or said sequential data memory to said formatter, a state address bus connected to said first memory circuit, said second memory circuit and said sequence controller, and a sequence address generator, said sequence address generator providing address information to said first memory circuit, said second memory circuit and said sequence controller via said state address bus.
Claim 2
Dependent Claim
169 words
Apparatus for providing high speed control of digital test patterns in automatic test equipment, said apparatus comprising, a first memory circuit including a data random access memory (RAM) storing data of nonsequential vectors, said data RAM having a first storage capacity, a second memory circuit including a sequential data memory storing blocks of data of sequential vectors, said sequential memory having more storage capacity than said first storage capacity, a formatter for receiving data from said data RAM or said sequential data memory and using the data to provide inputs to a circuit under test, a sequence controller controlling said first and second memory circuits for selectively routing data from said data RAM or said sequential data memory to said formatter, a state address bus connected to said first memory circuit, said second memory circuit and said sequence controller, and a sequence address generator, said sequence address generator providing address information to said first memory circuit, said second memory circuit and said sequence controller via said state address bus.
Claim 3
Dependent Claim
44 words
The apparatus of claim 1 wherein said data RAM comprises static RAMs, and said sequential data memory comprises a plurality of dynamic RAMs that are individually slower than said static RAMs, said dynamic RAMs having outputs that are combined to provide high-speed data transfer.
Claim 4
Dependent Claim
60 words
The apparatus of claim 2 wherein said sequential memory includes shift registers that are each connected to receive a multibit parallel output of a respective said dynamic RAM and to provide a serial shift register output, and said dynamic RAMs each provide a multibit word that corresponds to a single bit of data of a plurality of consecutive sequential vectors.
Claim 5
Dependent Claim
37 words
The apparatus of claim 2 wherein said data RAM has stored in it data of some sequential vectors prior to said blocks to permit said dynamic RAMs to be primed to provide data at a high speed.
Claim 6
Dependent Claim
74 words
The apparatus of claim 1 wherein said sequence controller includes said sequence address generator, said state address bus being connected to the sequence address generator, and said first memory circuit includes a first microcode RAM that is loaded with microcode for said first memory and is connected to receive addresses from said state address bus, said microcode for said first memory including instructions as to sourcing or not sourcing data in said data RAM.
Claim 7
Dependent Claim
54 words
The apparatus of claim 5 wherein said second memory circuit includes a second microcode RAM loaded with microcode for said second memory and connected to receive addresses from said state address bus, said microcode for said second memory including instructions as to sourcing or not sourcing, where to start sourcing, and preparation for sourcing.
Claim 8
Dependent Claim
40 words
The apparatus of claim 6 wherein said second memory circuit includes an instruction decoder connected to receive instructions from said second microcode RAM, and a memory address/control circuit and output buffers for said sequential data memory controlled by said decoder.
Claim 9
Dependent Claim
35 words
The apparatus of claim 1 further comprising, a timing set memory storing blocks of timing data corresponding to said blocks of data of sequential vectors, said timing set memory providing timing data to said formatter.
Claim 10
Independent Claim
167 words
A method of providing high-speed control of digital test patterns in an automatic circuit tester comprising preparing a virtual vector pattern containing nonsequential vectors and sequential vectors, preparing instructions for storing data of said nonsequential vectors in a data RAM of a first memory circuit and for storing blocks of data of sequential vectors in a sequential data memory of a second memory circuit, loading said data of said nonsequential vectors in said data RAM of said first memory circuit, loading said data of said sequential vectors in said sequential data memory of said second memory circuit, providing address information from a sequence address generator to said first memory circuit and said second memory circuit via a state address bus, said state address bus being connected to said first memory circuit, and said second memory circuit, and utilizing said address information in selectively routing data from said data RAM or said sequential data memory to a formatter for use in providing inputs to a circuit under test.
Claim 11
Independent Claim
167 words
A method of providing high-speed control of digital test patterns in an automatic circuit tester comprising preparing a virtual vector pattern containing nonsequential vectors and sequential vectors, preparing instructions for storing data of said nonsequential vectors in a data RAM of a first memory circuit and for storing blocks of data of sequential vectors in a sequential data memory of a second memory circuit, loading said data of said nonsequential vectors in said data RAM of said first memory circuit, loading said data of said sequential vectors in said sequential data memory of said second memory circuit, providing address information from a sequence address generator to said first memory circuit and said second memory circuit via a state address bus, said state address bus being connected to said first memory circuit, and said second memory circuit, and utilizing said address information in selectively routing data from said data RAM or said sequential data memory to a formatter for use in providing inputs to a circuit under test.
Claim 12
Dependent Claim
77 words
The method of claim 9 further comprising preparing first and second microcode for said first and second memory circuits so that data are respectively sourced from said data RAM or said sequential data memory in response to addresses on a state bus of said automatic circuit tester, and loading said first microcode in a first microcode RAM in said first memory circuit and loading said second microcode in a second microcode RAM in said second memory circuit.
Claim 13
Dependent Claim
37 words
The method of claim 9 wherein said virtual vector pattern has labels associated with some said nonsequential vectors to indicate the destination of a transfer and further comprising preparing a list of labels in a destination table.
Claim 14
Dependent Claim
17 words
The method of claim 11 further comprising preparing a list of transfers in a vector transfer table.
Claim 15
Dependent Claim
55 words
The method of claim 9 wherein said data RAM comprises static RAMs, and said sequential data memory comprises a plurality of dynamic RAMs that are individually slower than said static RAMs, and wherein said sourcing said data from said sequential data memory comprises combining the outputs of said dynamic RAMs to provide high-speed data transfer.
Claim 16
Dependent Claim
52 words
The method of claim 13 wherein said sourcing said data from said sequential data memory comprises inputting multibit words of said dynamic RAMs into shift registers, outputting said multibit words one bit at a time, and combining serial bit outputs of said shift registers to obtain multibit word outputs at high speed.
Claim 17
Dependent Claim
33 words
The method of claim 14 wherein each said dynamic RAM has a pair of said shift registers, a register of each pair inputting multibit words while the other is outputting and vice versa.
Claim 18
Dependent Claim
39 words
The method of claim 14 further comprising loading data of some sequential vectors prior to blocks of sequential data stored in said sequential memory to permit said dynamic RAMs to be primed to provide data at a high speed.
Claim 19
Dependent Claim
57 words
The method of claim 16 wherein said loading said data of sequential vectors comprises generating a starting address in said dynamic RAMs for the beginning of a said block of data of sequential data, said generating including combining portions of said starting address stored at consecutive addresses of a microcode RAM addressed by said state address bus.
Claim 20
Dependent Claim
48 words
The method of claim 9 further comprising, storing blocks of timing data in a timing set memory, said blocks of timing data corresponding to said blocks of data of sequential vectors, and providing said timing data to said formatter when selectively routing data from said sequential data memory.
Claim 21
Dependent Claim
35 words
The method of claim 9 wherein said preparing instructions includes generating a sequential table representative of blocks of said sequential vectors, where each entry in said table corresponds to a block of consecutive sequential vectors.
Claim 22
Dependent Claim
48 words
The method of claim 19 wherein said generating a sequential table further comprises including in each entry of said sequential table a start sequential vector corresponding to the first vector of said block and a size number representative of the number of said sequential vectors in said block.
Claim 23
Dependent Claim
69 words
The method of claim 20 wherein said generating a sequential table comprises retrieving a vector from said virtual vector pattern, determining whether said vector is a nonsequential vector or a sequential vector, incrementing said size number if said vector is a said sequential vector, and saving said size number if said vector is a said nonsequential vector and is the first said nonsequential vector after a said sequential vector,
Claim 24
Dependent Claim
32 words
The method of claim 21 wherein said generating a sequential table further comprises removing any said entry of said sequential table in which said size number is smaller than a predetermined size.
Claim 25
Dependent Claim
25 words
The method of claim 20 wherein said preparing instructions includes splitting said virtual vector pattern into sequential blocks and nonsequential blocks utilizing said sequential table.
Claim 26
Dependent Claim
35 words
The method of claim 23 wherein splitting further comprises assigning state numbers to vectors in said nonsequential blocks, said state numbers corresponding to state addresses provided on said state address bus of said automatic tester.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-16 | 1993-04-17 | 1993-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-16 | 1997-04-17 | 1997-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-16 | 2001-04-17 | 2001-10-17 | $7700.00 | Window Closed / Lapsed |