Low power voltage clamp circuit

Claim 2

An improved voltage clamping circuit for clamping a voltage at a predetermined voltage, said voltage clamping circuit having a power source terminal having a supply voltage coupled thereto, an output terminal and a reference terminal, comprising: voltage sensing and clamping means coupled between said output terminal of said voltage clamping circuit and said reference terminal for controlling the voltage appearing between said output terminal and said reference terminal, including means for developing and sensing said voltage and for clamping said voltage at a predetermined voltage; control circuit means coupled to said voltage sensing and clamping means for generating a control signal related to said voltage; and current generating means coupled to said control circuit means and connected between said power source terminal and said voltage sensing and clamping means for generating a current responsive to said control signal, said generated current being of sufficient magnitude to produce said voltage across said voltage sensing and clamping means.

Claim 3

The apparatus of claim 1 further including input means for disabling said current generating means in response to an input signal.

Claim 4

The apparatus of claim 1 wherein said reference terminal is coupled to a ground reference potential.

Claim 5

The apparatus of claim 1 wherein said voltage clamp circuit supply voltage is a positive voltage.

Claim 6

The apparatus of claim 1 wherein said voltage clamp circuit supply voltage is a negative voltage.

Claim 7

The apparatus of claim 1 wherein said voltage sensing and clamping means comprises a first diode having first and second terminals wherein said first terminal of said first diode is coupled to said output terminal of said voltage clamping means, a second diode having first and second terminals wherein said second terminal of said second diode is coupled to said reference terminal, and at least one series connected diode coupled between said second and first terminals of said first and second diodes, respectively.

Claim 8

The apparatus of claim 6 wherein each respective diode comprises an n-type enhancement mode transistor having a source, a drain, and a gate, and wherein said said first terminal comprises the source and gate of said transistor connected in common and said second terminal comprises the drain of said transistor.

Claim 9

The apparatus of claim 6 wherein each respective diode comprises a p-type enhancement mode transistor having a source, a drain, and a gate, and wherein said said first terminal comprises the drain and gate of said transistor connected in common and said second terminal comprises the source of said transistor.

Claim 10

The apparatus of claim 6 wherein said control circuit means comprises a p-type enhancement mode transistor having a gate, source and drain said p-type enhancement mode transistor disposed with its source coupled to said power source terminal, and its gate coupled to said output terminal of said voltage clamping means and an n-type enhancement mode transistor having a gate, source and drain said n-type enhancement mode transistor disposed with its source coupled to the drain of said p-type enhancement mode transistor, its drain coupled to said reference terminal and its gate coupled to said first terminal of said second diode.

Claim 11

The apparatus of claim 9 wherein said current generating means comprises a p-type enhancement mode transistor having a gate, source and gain said p-type enhancement mode transistor disposed with its gate coupled to said power source terminal, its source coupled to said power source terminal, and further comprising an n-type enhancement mode transistor having a gate, source and drain said n-type enhancement mode transistor disposed with its drain coupled to said output terminal of said voltage clamping means, its source coupled to the drain of said p-type enhancement mode transistor and its gate coupled to the source of said n-type enhancement mode transistor of said control circuit means.

Claim 12

The apparatus of claim 9 further including an input terminal, and wherein said current generating means comprises a p-type enhancement mode transistor having a gate, source and drain said p-type enhancement mode transistor disposed with its source coupled to said power source terminal and further comprising a first n-type enhancement mode transistor having gate, source and drain said n-type enhancement mode transistor disposed with its drain coupled to said output terminal of said voltage clamping means, its source coupled to the drain of said p-type enhancement mode transistor and its gate coupled to the source of said n-type enhancement mode transistor of said control circuit means and a second n-type enhancement mode transistor having a gate, source and drain said n-type enhancement mode transistor disposed with its drain coupled to said reference terminal of said voltage clamping means, its source coupled to the drain of said first n-type enhancement mode transistor and its gate coupled to the gate of said p-type enhancement mode transistor wherein this common gate connection comprises said input terminal of said voltage clamping means.

Claim 13

The apparatus of claim 1 wherein said current generating means comprises a transistor of a first conductivity type having a gate, source and drain said transistor of a first conductivity type disposed with its gate coupled to said power source terminal, its source coupled to said power source terminal and further comprising a transistor of a second conductivity type having a gate, source and drain said second transistor of a second conductivity type disposed with its drain coupled to said output terminal of said voltage clamping means, its source coupled to the drain of said transistor of said first conductivity type and its gate coupled to said control circuit means.

Claim 14

The apparatus of claim 12 wherein said transistor of a first conductivity type is a p-type enhancement mode transistor.

Claim 15

The apparatus of claim 12 wherein said transistor of a second conductivity type is a n-type enhancement mode transistor.

Claim 16

The apparatus of claim 1 further including an input terminal, and wherein said current generating means comprises a transistor of a first conductivity type having a gate, source and drain said transistor of a first conductivity type disposed with its source coupled to said power source terminal and further comprising a first transistor of a second conductivity type having gate, source and drain said first transistor of a second conductivity type disposed with its drain coupled to said output terminal of said voltage clamping means, its source coupled to the drain of said transistor of a first conductivity type and its gate coupled to said control circuit means and a second transistor of a second conductivity type having gate, source and drain said second transistor of a second conductivity type disposed with its drain coupled to said reference terminal of said voltage clamping means, its source coupled to the drain of said transistor of a first conductivity type and its gate coupled to the gate of said transistor of said first conductivity type wherein this common gate connection comprises said input terminal of said voltage clamping means.

Claim 17

The apparatus of claim 15 wherein said transistor of a first conductivity type is a p-type enhancement mode transistor.

Claim 18

The apparatus of claim 15 wherein said transistor of a second conductivity type is a n-type enhancement mode transistor.

Claim 19

The apparatus of claim 2 wherein said disabling means includes means for coupling said output terminal to said reference terminal and means for decoupling said power source terminal from said current generating means.

Claim 20

An improved current controlled voltage reference having a power source terminal having a supply voltage coupled thereto, an output terminal and a reference terminal, comprising: voltage sensing and clamping means coupled between said output terminal of said voltage sensing and clamping circuit and said reference terminal for controlling the voltage appearing between said output terminal and said reference terminal, including means for developing and sensing said voltage and for clamping said voltage at a predetermined voltage; control circuit means coupled to said voltage sensing and clamping means for generating a control signal related to said voltage; and current generating means coupled to said control circuit means and connected between said power source terminal and said voltage sensing and clamping means for generating a current responsive to said control signal, said generated current being of sufficient magnitude to produce said voltage across said voltage sensing and clamping means.

Claim 21

An improved current controlled voltage reference having a power source terminal having a supply voltage coupled thereto, an output terminal and a reference terminal, comprising: voltage sensing and clamping means coupled between said output terminal of said voltage sensing and clamping circuit and said reference terminal for controlling the voltage appearing between said output terminal and said reference terminal, including means for developing and sensing said voltage and for clamping said voltage at a predetermined voltage; control circuit means coupled to said voltage sensing and clamping means for generating a control signal related to said voltage; and current generating means coupled to said control circuit means and connected between said power source terminal and said voltage sensing and clamping means for generating a current responsive to said control signal, said generated current being of sufficient magnitude to produce said voltage across said voltage sensing and clamping means.

Claim 22

An improved voltage clamping circuit for clamping positive and negative voltages at predetermined voltages, said voltage clamping circuit including a positive power source terminal having a positie supply voltage coupled thereto, a negative power source terminal having a negative supply voltage coupled thereto, an output terminal and a reference terminal, comprising: positive and negative voltage sensing and clamping means coupled between said output terminal of said voltage clamping circuit and said reference terminal for for controlling the voltage appearing between said output terminal and said reference terminal, including means for developing and sensing a selected one of said positive and negative voltages and for clamping said selected voltage at a predetermined voltage; first and second control circuit means coupled to said positive and negative voltage sensing and clamping means for generating first and second control signals respectively said first control signal related to said positive voltage and said second control signal related to said negative voltage; first and second current generating means coupled to said first and second control circuit means respectively for generating first and second control currents in inverse proportion to said first and second control signals, respectively, said first current generating means coupled between said positive power source terminal and said positive voltage sensing and clamping means, said second current generating means coupled between said negative power source terminal and said negative voltage sensing and clamping means, said generated currents each being of sufficient magnitude to produce said selected positive or negative voltage across said positive and negative voltage sensing and clamping means; and means for disabling a selected one of said first and second current generating means.

Claim 23

An improved voltage clamping circuit for clamping positive and negative voltages at predetermined voltages, said voltage clamping circuit including a positive power source terminal having a positie supply voltage coupled thereto, a negative power source terminal having a negative supply voltage coupled thereto, an output terminal and a reference terminal, comprising: positive and negative voltage sensing and clamping means coupled between said output terminal of said voltage clamping circuit and said reference terminal for for controlling the voltage appearing between said output terminal and said reference terminal, including means for developing and sensing a selected one of said positive and negative voltages and for clamping said selected voltage at a predetermined voltage; first and second control circuit means coupled to said positive and negative voltage sensing and clamping means for generating first and second control signals respectively said first control signal related to said positive voltage and said second control signal related to said negative voltage; first and second current generating means coupled to said first and second control circuit means respectively for generating first and second control currents in inverse proportion to said first and second control signals, respectively, said first current generating means coupled between said positive power source terminal and said positive voltage sensing and clamping means, said second current generating means coupled between said negative power source terminal and said negative voltage sensing and clamping means, said generated currents each being of sufficient magnitude to produce said selected positive or negative voltage across said positive and negative voltage sensing and clamping means; and means for disabling a selected one of said first and second current generating means.

Claim 24

The apparatus of claim 20 further including input means for disabling said selected one of said first and second current generating means in response to an input signal.

Claim 25

The apparatus of claim 20 wherein said reference terminal is coupled to a ground reference potential.

Claim 26

The apparatus of claim 1 wherein said positive voltage sensing and clamping means comprises a first diode having first and second terminals wherein said first terminal of said first diode is coupled to said output terminal of said voltage clamping means, a second diode having first and second terminals wherein said second terminal of said second diode is coupled to said reference terminal and at least one series connected diode coupled between said second and first terminals of said first and second diodes, respectively.

Claim 27

The apparatus of claim 23 wherein each respective diode comprises an n-type enhancement mode transistor having a source, a drain, and a gate, and wherein said said first terminal comprises the source and gate of said transistor connected in common and said second terminal comprises the drain of said transistor.

Claim 28

The apparatus of claim 20 wherein said negative voltage sensing and clamping means comprises a first diode having first and second terminals wherein said first terminal of said first diode is coupled to said output terminal of said voltage clamping means, a second diode having first and second terminals wherein said second terminal of said second diode is coupled to said reference terminal and at least one series connected diode coupled between said second and first terminals of said first and second diodes, respectively.

Claim 29

The apparatus of claim 23 wherein each respective diode comprises a p-type enhancement mode transistor having a source, a drain, and a gate, and wherein said said first terminal comprises the drain and gate of said transistor connected in common and said second terminal comprises the source of said transistor.

Claim 30

The apparatus of claim 23 wherein said first control circuit means comprises a p-type enhancement mode transistor having a gate, source and drain said p-type enhancement mode transistor disposed with its source coupled to said positive power source terminal, and its gate coupled to said output terminal of said voltage clamping means and an n-type enhancement mode transistor having a gate, source and drain said n-type enhancement mode transistor disposed with its source coupled to the drain of said p-type enhancement mode transistor, its drain coupled to said reference terminal and its gate coupled to said first terminal of said second diode.

Claim 31

The apparatus of claim 25 wherein said second control circuit means comprises an n-type enhancement mode transistor having a gate, source and drain said n-type enhancement mode transistor disposed with its drain coupled to said negative power source terminal, and its gate coupled to said output terminal of said voltage clamping means and a p-type enhancement mode transistor having a gate, source and drain said p-type enhancement mode transistor disposed with its drain coupled to the source of said n-type enhancement mode transistor, its source coupled to said reference terminal and its gate coupled to said first terminal of said second diode.

Claim 32

The apparatus of claim 27 wherein said first current generating means comprises a p-type enhancement mode transistor having a gate, source and drain said p-type enhancement mode transistor disposed with its source coupled to said positive power source terminal and its gate coupled to a first control terminal, and further comprising an n-type enhancement mode transistor having a gate, source and drain said n-type enhancement mode transistor disposed with its drain coupled to said output terminal of said voltage clamping means, its source coupled to the drain of said p-type enhancement mode transistor and its gate coupled to source of said n-type enhancement mode transistor of said first control circuit means.

Claim 33

The apparatus of claim 28 wherein said second current generating means comprises a n-type enhancement mode transistor having a gate, source and drain said n-type enhancement mode transistor disposed with its drain coupled to said negative power source terminal, and its gate coupled to a second control terminal, and further comprising a p-type enhancement mode transistor having gate, source and drain said p-type enhancement mode transistor disposed with its source coupled to output terminal of said voltage clamping means its drain coupled to the source of said n-type enhancement mode transistor, and its gate coupled to the source of said n-type enhancement mode transistor of said second control circuit means.

Claim 34

The apparatus of claim 29 wherein said first control terminal of said first current generating means is coupled to said positive power source terminal.

Claim 35

The apparatus of claim 30 wherein said first control terminal of said second current generating means is coupled to said negative power source terminal.

Claim 36

The apparatus of claim 21 wherein said input means comprises: an input terminal for receiving a input signal; an inverter having an input and an output, wherein the input to said inverter is coupled to said input terminal and the output of said inverter is coupled to said first current generating means; and an n-type enhancement transistor means having a gate source and drain wherein said gate is coupled to said negative power source terminal, its source is coupled to said output of said inverter and its drain is coupled to said second current generating means.