Multiple processor accelerator for logic simulation

Claim 1

A computer system coupled to a plurality of users for implementing an event driven algorithm of each of the users, comprising: (1) a master processor coupled to the users for providing overall control of the computer system and executing the event driven algorithm of each of the users, the master processor further including a master memory; (2) a unidirectional ring bus coupled to the master processor; (3) a plurality of processor modules coupled to the unidirectional ring bus which transfers data among the processor modules and the master processor, each of the processor modules capable of receiving into a plurality of connectors a plurality of selectable simulation processors for independently operating on a portion of the event driven algorithm and functioning substantially simultaneously to each other, each simulation processor including a simulation memory for storing the simulation data for circuit elements being simulated by that processor, the plurality of selectable processor including (i) a hardwired processor for providing rapid simulation of simpler circuit elements and (ii) a microcodable processor for providing simulation of more complicated circuit elements, each of the processor modules further including: (a) an interprocessor bus coupled to the plurality of processors within the module for transferring the simulation data among the processors; (b) an interface means coupled to the unidirectional bus and interprocessor bus for transferring the simulation data between the unidirectional bus and the interprocessor bus, the interface means including (i) a first storage means for storing data from the ring bus that is destined for a processor of the plurality of processors of the module; (ii) a second storage means for storing data from the simulation processor that is destined for transfer external to the module; and (iii) a bypass means for bypassing data on the ring bus that is not destined for the module; wherein intra-module transfer of data on the interprocessor bus occurs independently of transfer of data on the unidirectional bus.