MIS FET and process of fabricating the same

Claim 2

An LDD MIS field effect transistor formed at the surface of a silicon substrate, comprising a channel region in part of the substrate; a gate insulating film formed on the channel region; a gate electrode formed on the gate insulating film; a lightly-doped region formed in the substrate adjacent to an end of the channel region; a heavily-doped region formed in the substrate, said heavily-doped region being separated from the channel region by the lightly-doped region; a metal silicide film formed on part of the lightly-doped region and the heavily doped region; and a sidewall spacer formed on a side of the gate electrode, said sidewall spacer being used as a mask during ion implantation for forming said heavily-doped region, such that said metal silicide separates said sidewall spacer from the substrate.

Claim 3

A transistor according to claim 1, wherein the metal silicide is a silicide of a refractory metal.

Claim 4

A transistor according to claim 1, wherein the metal silicide is platinum silicide, titanium silicide, tungsten silicide, or molybdenum silicide.

Claim 5

A transistor according to claim 1, wherein the impurity used for the formation of the doped regions is an N-type impurity.

Claim 6

A transistor according to claim 1, wherein the metal silicide is a silicide of a metal that has a melting point of at least 1,650 degrees Centigrade.

Claim 7

A lightly-doped drain/source MIS field effect transistor formed in a semiconductor substrate, comprising: a gate insulating film formed on the substrate; a gate electrode formed on the gate insulating film; first and second lightly-doped regions formed in the substrate adjacent opposite portions of said gate electrode; first and second heavily-doped regions formed in the substrate, each of said first and second heavily-doped regions being separated from a respective opposite portion of said gate electrode by a corresponding lightly-doped region; first and second sidewall spacers each formed on the gate insulating film and on a respective opposite portion of said gate electrode; and first and second metal silicide films each disposed between a respective sidewall spacer and said substrate thereby preventing depletion of said lightly-doped regions.

Claim 8

A lightly-doped drain/source MIS field effect transistor formed in a semiconductor substrate, comprising: a gate insulating film formed on the substrate; a gate electrode formed on the gate insulating film; first and second lightly-doped regions formed in the substrate adjacent opposite portions of said gate electrode; first and second heavily-doped regions formed in the substrate, each of said first and second heavily-doped regions being separated from a respective opposite portion of said gate electrode by a corresponding lightly-doped region; first and second sidewall spacers each formed on the gate insulating film and on a respective opposite portion of said gate electrode; and first and second metal silicide films each disposed between a respective sidewall spacer and said substrate thereby preventing depletion of said lightly-doped regions.