Patent US5220651A successfully refreshed from Google Patents.
US4872142A
Expired / Lapsed
US
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Semiconductor memory device with improved bit line arrangement
Assignee: Micron Memory Japan Ltd
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Filing: 1987-10-21
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Granted: 1989-10-03
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Expires: 2007-10-21
Abstract
Abstract A dynamic type semiconductor memory device with an improved bit line arrangement is disclosed. The memory device comprises at least first and second pairs of bit lines and a sense amplifier having a pair of input terminals to which one pair of bit lines among the first and second bit line pairs are selectively connected, and is featured in that the bit lines of the first bit line pair and the bit lines of the second bit line pair are alternately arranged in parallel.
Inventors
- 👤 Seiichi Hannai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:55
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; G11C7/00; G11C7/18
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
364 words
A semiconductor memory device comprising: first to fourth bit lines arranged consecutively in parallel, said second and third bit lines being located between said first and fourth bit lines, said second bit line being located between said first and third bit lines, said third bit line being located between said second and fourth bit lines; first to fourth memory cells coupled to said first to fourth bit lines, respectively; first to fourth word lines coupled to said first to fourth memory cells, respectively, enablement of said first word line and said first to fourth bit lines providing read out of only said first memory cell, enablement of said second word line and said first to fourth bit lines providing read out of only said second memory cell, enablement of said third word line and said first to fourth bit lines providing read out of only said third memory cell, enablement of said fourth word line and said first to fourth bit lines providing read out of only said fourth memory cell; a sense amplifier having a pair of input terminals; means for selecting one of said word lines; a first transfer circuit for simultaneously connecting said first and third bit lines to said pair of input terminals of said sense amplifiers; a second transfer circuit for simultaneously connecting said second and fourth bit lines to said pair of input terminals; and means for enabling said first transfer circuit to thereby amplify a signal difference between said first and third bit lines by said sense amplifier when one of said first and third word lines is selected by said selecting means, and for enabling said second transfer circuit to thereby amplify a signal difference between said second and fourth bit lines when one of said second and fourth word lines is selected by said selecting means, said second and fourth bit lines not being provided with a signal from any one of the memory cells when one of said first and third word lines is selected, said first and third bit lines not being provided a signal from any one of the memory cells when one of said second and fourth word lines is selectd.
Claim 2
Dependent Claim
364 words
A semiconductor memory device comprising: first to fourth bit lines arranged consecutively in parallel, said second and third bit lines being located between said first and fourth bit lines, said second bit line being located between said first and third bit lines, said third bit line being located between said second and fourth bit lines; first to fourth memory cells coupled to said first to fourth bit lines, respectively; first to fourth word lines coupled to said first to fourth memory cells, respectively, enablement of said first word line and said first to fourth bit lines providing read out of only said first memory cell, enablement of said second word line and said first to fourth bit lines providing read out of only said second memory cell, enablement of said third word line and said first to fourth bit lines providing read out of only said third memory cell, enablement of said fourth word line and said first to fourth bit lines providing read out of only said fourth memory cell; a sense amplifier having a pair of input terminals; means for selecting one of said word lines; a first transfer circuit for simultaneously connecting said first and third bit lines to said pair of input terminals of said sense amplifiers; a second transfer circuit for simultaneously connecting said second and fourth bit lines to said pair of input terminals; and means for enabling said first transfer circuit to thereby amplify a signal difference between said first and third bit lines by said sense amplifier when one of said first and third word lines is selected by said selecting means, and for enabling said second transfer circuit to thereby amplify a signal difference between said second and fourth bit lines when one of said second and fourth word lines is selected by said selecting means, said second and fourth bit lines not being provided with a signal from any one of the memory cells when one of said first and third word lines is selected, said first and third bit lines not being provided a signal from any one of the memory cells when one of said second and fourth word lines is selectd.
Claim 3
Dependent Claim
65 words
The memory device according to claim 1, wherein said first transfer circuit includes a pair of first transistors coupled between said first and third bit lines and said pair of input terminals of said sense amplifier, and said second transfer circuit includes a pair of second transistors coupled between said second and fourth bit lines and said pair of input terminals of said sense amplifier.
Claim 4
Dependent Claim
36 words
The memory device according to claim 1, further comprising means for operatively precharging said first to fourth bit lines to a predetermined potential before said selecting means selects one of said first to fourth word lines.
Claim 5
Dependent Claim
55 words
The memory device according to claim 1, further comprising a pair of bus lines, a first column selection circuit for operatively connecting said first and third bit lines to said pair of bus lines, and a second column selection circuit for operatively connecting said second and fourth bit lines to said pair of bus lines.
Claim 6
Dependent Claim
457 words
A semiconductor memory device comprising: first to fourth bit lines arranged consecutively in parallel, said second and third bit lines being located between said first and fourth bit lines, said second bit line being located between said first and third bit lines, said third bit line being located between said second and fourth bit lines; first to fourth memory cells coupled to said first to fourth bit lines, respectively; first to fourth word lines coupled to said first to fourth memory cells, respectively, enablement of said first word line and said first to fourth bit lines providing read out of only said first memory cell, enablement of said second word line and said first to fourth bit lines providing read out of only said second memory cell, enablement of said third word line and said first to fourth bit lines providing read out of only said third memory cell, enablement of said fourth word line and said first to fourth bit lines providing read out of only said fourth memory cell; a sense amplifier having a pair of input terminals; means for selecting one of said word lines; a first transfer circuit for simultaneously connecting said first and third bit lines to said pair of input terminals of said sense amplifiers; a second transfer circuit for simultaneously connecting said second and fourth bit lines to said pair of input terminals. means for enabling said first transfer circuit to thereby amplify a signal difference between said first and third bit lines by said sense amplifier when one of said first and third word lines is selected by said selecting means, and for enabling said second transfer circuit to thereby amplify a signal difference between said second and fourth bit lines when one of said second and fourth word lines is selected by said selecting means, said second and fourth bit lines not being provided with a signal from any one of the memory cells when one of said first and third word lines is seleted, said first and third bit lines not being provided with a signal from any one of the memory cells when one of said second and fourth word lines is selected; first to fourth dummy cells coupled to said first to fourth bit lines, respectively; first to fourth dummy word lines coupled to said first to fourth dummy cells, respectively; and means for selecting one of said dummy word lines, said third dummy word line being selected when said first word line is selected, said first dummy word line being selected when said third word line is selected, said fourth dummy word line being selected when said second word line is selected, said second dummy word line being selected when said fourth is selected.
Claim 7
Dependent Claim
457 words
A semiconductor memory device comprising: first to fourth bit lines arranged consecutively in parallel, said second and third bit lines being located between said first and fourth bit lines, said second bit line being located between said first and third bit lines, said third bit line being located between said second and fourth bit lines; first to fourth memory cells coupled to said first to fourth bit lines, respectively; first to fourth word lines coupled to said first to fourth memory cells, respectively, enablement of said first word line and said first to fourth bit lines providing read out of only said first memory cell, enablement of said second word line and said first to fourth bit lines providing read out of only said second memory cell, enablement of said third word line and said first to fourth bit lines providing read out of only said third memory cell, enablement of said fourth word line and said first to fourth bit lines providing read out of only said fourth memory cell; a sense amplifier having a pair of input terminals; means for selecting one of said word lines; a first transfer circuit for simultaneously connecting said first and third bit lines to said pair of input terminals of said sense amplifiers; a second transfer circuit for simultaneously connecting said second and fourth bit lines to said pair of input terminals. means for enabling said first transfer circuit to thereby amplify a signal difference between said first and third bit lines by said sense amplifier when one of said first and third word lines is selected by said selecting means, and for enabling said second transfer circuit to thereby amplify a signal difference between said second and fourth bit lines when one of said second and fourth word lines is selected by said selecting means, said second and fourth bit lines not being provided with a signal from any one of the memory cells when one of said first and third word lines is seleted, said first and third bit lines not being provided with a signal from any one of the memory cells when one of said second and fourth word lines is selected; first to fourth dummy cells coupled to said first to fourth bit lines, respectively; first to fourth dummy word lines coupled to said first to fourth dummy cells, respectively; and means for selecting one of said dummy word lines, said third dummy word line being selected when said first word line is selected, said first dummy word line being selected when said third word line is selected, said fourth dummy word line being selected when said second word line is selected, said second dummy word line being selected when said fourth is selected.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-02 | 1993-04-03 | 1993-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-02 | 1997-04-03 | 1997-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-02 | 2001-04-03 | 2001-10-03 | $7700.00 | Window Closed / Lapsed |