Multiple processor accelerator for logic simulation

Claim 1

A computer system coupled to a plurality of users for implementing an event driven algorithm of each of the users, comprising: (1) a master processor coupled to the users for providing overall control of the computer system and for executing the event driven algorithm of each of the users, wherein the master processor further includes a master memory; (2) a unidirectional ring bus coupled to the master processor; (3) a plurality of processor modules coupled to the unidirectional ring bus, wherein the unidirectional ring bus transfers data among the processor modules and the master processor, and wherein each processor module includes: (a) a plurality of simulation processors for independently operating on a portion of the event driven algorithm, wherein the plurality of simulation processors function substantially simultaneously to each other, and wherein each simulation processor further includes a simulation memory for storing simulation data for circuit elements being simulated by that respective simulation processor; (b) an interprocessor bus coupled to the plurality of simulation processors for transferring the simulation data among the plurality of simulation processors; (c) an interface means coupled to the unidirectional bus and the interprocessor bus for transferring the simulation data between the unidirectional bus and the interprocessor bus, wherein the interface means further includes: (i) an event memory that stores a history of event changes of the circuit elements being simulated by the simulation processors of that respective processor module; (ii) a first storage means for storing data for the ring bus that is destined for a simulation processor of the simulation processors of that respective processor module; (iii) a second storage means for storing data from a simulation processor of the simulation processors of that respective module, wherein the data is destined for transfer to the ring bus; (vi) a reference table for storing a logical address for each of the simulation processors of that respective processor module, wherein the reference table is accessed to determine if that respective processor module is a destination of simulation data arriving on the ring bus; wherein an intramodule transfer of data on the interprocessor bus occurs independently of a transfer of data on the unidirectional bus.