US4870660A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Variable frequency rate receiver
Assignee: Unisys Corp
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Filing: 1987-12-28
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Granted: 1989-09-26
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Expires: 2007-12-28
Abstract
Abstract A variable data rate receiver is provided which employs a novel phase locked loop (PLL) of the type employing a data detection loop and a tracking loop. The data detection loop is initially not coupled to the input of the voltage controlled oscillator in the tracking loop of the PLL, but is separated by an electronic switch. A phase lock detection circuit is provided which is coupled to the data detection loop and to the tracking loop for detecting the difference in the voltage error signals in the data detection loop and the tracking loop. When this error signal indicates that the tracking loop is locked on to the carrier signal the electronic switch is closed completing the phase locked loop circuit after lock on of the carrier is achieved.
Inventors
- 👤 Christopher R. Keate
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:18
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/227; H04L27/2271; H04L27/2273
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
176 words
A variable rate receiver for receiving phase shift key (PSK) data signals as an input data stream and producing drift free real time in-phase data signals at the output comprising: a tracking loop of the type including a voltage controlled oscillator coupled to said input data stream for producing a signal at the frequency of the carrier, a data detection loop coupled to said input data stream for producing real time data output signals, a comparator coupled to said data detection loop for detecting data transactions, electronic switch means coupled between said comparator and said tracking loop, phase lock detection means coupled to said electronic switch means and to said tracking loop and to said data detection loop for detecting when the voltage error signals in said tracking loop and in said data detection loop have reached a predetermined voltage difference indicating that the tracking loop is locked on to the phase and frequency of the carrier of the input data stream, and said phase lock detection means having means for closing said electronic switch means.
Claim 2
Dependent Claim
176 words
A variable rate receiver for receiving phase shift key (PSK) data signals as an input data stream and producing drift free real time in-phase data signals at the output comprising: a tracking loop of the type including a voltage controlled oscillator coupled to said input data stream for producing a signal at the frequency of the carrier, a data detection loop coupled to said input data stream for producing real time data output signals, a comparator coupled to said data detection loop for detecting data transactions, electronic switch means coupled between said comparator and said tracking loop, phase lock detection means coupled to said electronic switch means and to said tracking loop and to said data detection loop for detecting when the voltage error signals in said tracking loop and in said data detection loop have reached a predetermined voltage difference indicating that the tracking loop is locked on to the phase and frequency of the carrier of the input data stream, and said phase lock detection means having means for closing said electronic switch means.
Claim 3
Dependent Claim
26 words
A variable rate receiver as set forth in claim 1 which further includes a high-speed multiplier in said phase locked loop coupled to said electronic switch.
Claim 4
Dependent Claim
45 words
A variable rate receiver as set forth in claim 1 wherein said phase locked loop comprises a high-speed multiplier coupled to the input of a loop filter, and the output of said loop filter being coupled to the voltage controlled oscillator of said tracking loop.
Claim 5
Dependent Claim
23 words
A variable rate receiver as set forth, in claim 3 wherein said electronic switch is connected between said high-speed multiplier and said comparator.
Claim 6
Dependent Claim
20 words
A variable rate receiver as set forth in claim 1 which further includes an amplifier in said input data stream.
Claim 7
Dependent Claim
45 words
A variable rate receiver as set forth in claim 1 wherein said input data stream comprises a data free portion of carrier signal having a length in bits predetermined to be sufficient to cause said phase lock detection means to close said electronic switch means.
Claim 8
Dependent Claim
33 words
A variable rate received as set forth in claim 6 wherein said input data stream is provided with periodic data free portions of carrier signals for resynchronizing the phase of said incoming signals.
Claim 9
Dependent Claim
53 words
A variable rate receiver as set forth in claim 1 wherein said tracking loop and said data detection loop each comprise low pass filter means, a bit synchronizer, and means for changing the frequency of said low pass filters and for varying the frequency of said bit synchronizer in said data detection loop.
Claim 10
Dependent Claim
36 words
A variable rate receiver as set forth in claim 8 wherein said means for changing the frequency of said low pass filters comprises a processor controller coupled to programmable resistor packs in said low pass filters.
Claim 11
Dependent Claim
21 words
A variable rate receiver as set forth in claim 9 which further includes a programmable clock coupled to said processor controller.
Claim 12
Dependent Claim
26 words
A variable rate receiver as set forth in claim 1 which further includes a bit synchronizer in said data detection loop comprising an early-late gate circuit.
Claim 13
Dependent Claim
24 words
A variable rate receiver as set forth in claim 11 wherein such early-late gate circuit comprises sample and hold circuits and absolute value detectors.
Claim 14
Dependent Claim
25 words
A variable rate receiver as set forth in claim 12 which further includes a differential amplifier coupled to the output of said absolute value detectors.
Claim 15
Dependent Claim
31 words
A variable rate receiver as set forth in claim 13 which further includes delay circuit means coupled to the output of said programmable clock and to said sample and hold circuits.
Claim 16
Dependent Claim
24 words
A variable rate receiver as set forth in claim 9 wherein said programmable clock comprises a digital synthesizer clock coupled to said processor controller.
Claim 17
Independent Claim
118 words
A method of decreasing the acquisition time in a variable data rate receiver which employs a phase lock loop circuit having a data detection loop and a tracking loop, comprising the steps of: isolating said data detection loop from said tracking loop at the input to the tracking loop, providing an electronic switch at the input of said tracking loop, detecting the difference between the error voltage signal in said data detection loop and said tracking loop, closing said electronic switch between said data detection loop and said tracking loop to reconnect as an operable circuit the phase lock loop when the error voltage signal difference indicates that the tracking loop is locked on to the carrier signal.
Claim 18
Independent Claim
118 words
A method of decreasing the acquisition time in a variable data rate receiver which employs a phase lock loop circuit having a data detection loop and a tracking loop, comprising the steps of: isolating said data detection loop from said tracking loop at the input to the tracking loop, providing an electronic switch at the input of said tracking loop, detecting the difference between the error voltage signal in said data detection loop and said tracking loop, closing said electronic switch between said data detection loop and said tracking loop to reconnect as an operable circuit the phase lock loop when the error voltage signal difference indicates that the tracking loop is locked on to the carrier signal.
Claim 19
Dependent Claim
43 words
A method as set forth in claim 16 which further includes providing a burst of carrier tone signals as a preamble to the data stream input to said phase lock loop to further enhance the speed of acquisition of said carrier tone signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-25 | 1993-03-27 | 1993-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-25 | 1997-03-27 | 1997-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-25 | 2001-03-27 | 2001-09-26 | $7700.00 | Window Closed / Lapsed |