Patent US4870622A successfully refreshed from Google Patents.
US4870622A
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DRAM controller cache
Assignee: Advanced Micro Devices Inc
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Filing: 1988-06-24
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Granted: 1989-09-26
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Expires: 2008-06-24
Abstract
Abstract A method of minimizing memory access time on a memory with multiplexed address inputs between data stored in locations in memory in the same row but in different columns. First data is accessed at a predetermined column and row location. The predetermined row location of the first data is then recorded. The location of second data is then recorded. Then the locations of the first and second data are compared. A row compare signal is generated if the row value of both first and second data are identical. Only the column address is varied in response to the row compare signal.
Inventors
- 👤 Percy R. Aria
- 👤 Sherman Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:01
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G06; G06F; G06F12/00; G06F12/02; G06F12/0215; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
138 words
A method of minimizing memory access time on a memory with multiplexed address inputs between data stored in locations in memory in the same row but in different columns, the steps comprising: (a) accessing first data at a predetermined column and row location; (b) recording said predetermined row location of said first data; (c) recording the row location of second data; (d) comparing row locations of said first and said second data; (e) generating a row compare signal and maintaining a row address strobe in a charged state to eliminate the necessity for strobe precharging when accessing said second data if said row locations of both first and second data are identical; and (f) varying only said column address to said memory in response to said row compare signal, said varying step initiating access of said second data.
Claim 2
Independent Claim
138 words
A method of minimizing memory access time on a memory with multiplexed address inputs between data stored in locations in memory in the same row but in different columns, the steps comprising: (a) accessing first data at a predetermined column and row location; (b) recording said predetermined row location of said first data; (c) recording the row location of second data; (d) comparing row locations of said first and said second data; (e) generating a row compare signal and maintaining a row address strobe in a charged state to eliminate the necessity for strobe precharging when accessing said second data if said row locations of both first and second data are identical; and (f) varying only said column address to said memory in response to said row compare signal, said varying step initiating access of said second data.
Claim 3
Dependent Claim
38 words
The method in accordance with claim 1, further comprising the steps of: (g) updating a storage register with the address of said second data when said comparison of locations of said first and second data is not identical.
Claim 4
Dependent Claim
22 words
The method in accordance with claim 1, wherein during said step of accessing first data, a row address strobe signal is enabled.
Claim 5
Dependent Claim
24 words
The method in accordance with claim 3, wherein during said step of varying only said column address, said row address strobe signal is maintained.
Claim 6
Dependent Claim
19 words
The method in accordance with claim 4, wherein said row address strobe signal is maintained by a timing generator.
Claim 7
Dependent Claim
30 words
The method in accordance with claim 4, wherein said row address strobe signal is disabled when said comparison of row locations of said first and second data is not identical.
Claim 8
Independent Claim
149 words
A method of minimizing memory access time on a memory with multiplexed address inputs between data stored in locations in memory in the same bank and row but in different columns, the steps comprising: (a) accessing first data at a predetermined bank, column and row location; (b) recording said predetermined bank and row locations of said first data; (c) recording the bank and row locations of second data; (d) comparing bank and row locations of said first and said second data; (e) generating a compare signal and maintaining a row address strobe in a charged state to eliminate the necessity for strobe precharging when addressing said second data if said bank and said row values of both said first and second data are identical; and (f) varying only said column address to said memory in response to said compare signal, said varying step initiating access of said second data.
Claim 9
Independent Claim
149 words
A method of minimizing memory access time on a memory with multiplexed address inputs between data stored in locations in memory in the same bank and row but in different columns, the steps comprising: (a) accessing first data at a predetermined bank, column and row location; (b) recording said predetermined bank and row locations of said first data; (c) recording the bank and row locations of second data; (d) comparing bank and row locations of said first and said second data; (e) generating a compare signal and maintaining a row address strobe in a charged state to eliminate the necessity for strobe precharging when addressing said second data if said bank and said row values of both said first and second data are identical; and (f) varying only said column address to said memory in response to said compare signal, said varying step initiating access of said second data.
Claim 10
Dependent Claim
38 words
The method in accordance with claim 7, further comprising the step of: (g) updating a storage register with the address of said second data when said comparison of location of said first and second data is not identical.
Claim 11
Dependent Claim
22 words
The method in accordance with claim 7, wherein during said step of accessing first data, a row address strobe signal is enabled.
Claim 12
Dependent Claim
24 words
The method in accordance with claim 9, wherein during said step of varying only said column address, said row address strobe signal is maintained.
Claim 13
Dependent Claim
19 words
The method in accordance with claim 10, wherein said row address strobe signal is maintained by a timing generator.
Claim 14
Dependent Claim
29 words
The method in accordance with claim 10, wherein said row address strobe signal is disabled when said comparison of locations of said first and second data is not identical.
Claim 15
Dependent Claim
13 words
The method in accordance with claim 1 wherein said memory is a DRAM.
Claim 16
Dependent Claim
15 words
The method in accordance with claim 13 wherein said DRAM is a page mode DRAM.
Claim 17
Dependent Claim
16 words
The method in accordance with claim 13 wherein said DRAM is a fast page mode DRAM.
Claim 18
Dependent Claim
15 words
The method in accordance with claim 13 wherein said DRAM is a nibble mode DRAM.
Claim 19
Dependent Claim
13 words
The method in accordance with claim 7 wherein said memory is a DRAM.
Claim 20
Dependent Claim
15 words
The method in accordance with claim 17 wherein said DRAM is a page mode DRAM.
Claim 21
Dependent Claim
16 words
The method in accordance with claim 17 wherein said DRAM is a fast page mode DRAM.
Claim 22
Dependent Claim
15 words
The method in accordance with claim 17 wherein said DRAM is a nibble mode DRAM.
References Cited (Backward Citations)
US4725945A
Cited
US4803621A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-25 | 1993-03-27 | 1993-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-25 | 1997-03-27 | 1997-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-25 | 2001-03-27 | 2001-09-26 | $7700.00 | Window Closed / Lapsed |