Method for simulating an open fault in a logic circuit comprising field effect transistors and simulation models for implementing the method

Claim 3

The method of claim 1, comprising the additional step of: upon termination of the through-connection of the preceding signal, replacing the preceding signal with a signal resulting from a fault-free simulation of the logic circuit.

Claim 4

The method of claim 2, wherein: said predetermined time in one clock period so that the maintenance of the through-connection of the preceding signal is terminated by a single, further signal at the circuit point influenced by the stuck-open fault.

Claim 5

A method as claimed in claim 1, wherein the step of maintaining the through-connection of the immediately preceding signal is further defined by the steps of; counting the number of clock periods in which a signals influenced by a stuck-open fault persists; comparing the number of counted periods with a fixed count; and terminating maintenance of the preceding signal if and when the number of counted periods exceeds said fixed count.

Claim 6

A method as claimed in claim 4 comprising additional step of: setting said fixed count at one clock period.

Claim 7

A stimulation model for simulating a stuck-open fault in a logic circuit which comprises field effect transistors, and in which output bit patterns are derived from a sequence of input bit patterns respectively applied in successive clock periods to the simulation model containing the stuck-open fault, the output bit patterns being compared to reference patterns valid for fault-free operation of said logic circuit, said model comprising: a simulation stage means for simulating the stuck-open fault in said logic circuit; an output stage means connected to said simulation stage for simulating a logic circuit affected by the stuck-open fault, said simulation stage means including first and second outputs connected to said output stage means and said output stage means including an output, sad output stage including means responsive to a signal appearing at said first output of said simulation stage which is not influenced by the stuck-open fault for through-connecting said signal to said output of said output stage means and responsive to a signal at said first output of said simulation stage which is influenced by the stuck-open fault through-connecting a preceding signal not influenced by said stuck-open fault which has appeared immediately therebefore; a detector means connected to said first and second outputs of said simulation stage means for producing an output signal in response to a signal at said first and second outputs indicating a stuck-open fault; a resettable counter connected to said detector means and including a clock input for receiving clock pulses corresponding to said clock periods, said resettable counter being enable by the output signal of said detector means to add clock pulses received via the clock input; a comparator including a first input connected to said counter to receive the counter contents and a second input for receiving a limit value corresponding to a maximum persistence time of said output signal in successive clock periods to be compared in said comparator to the counter contents, and an output at which a switching signal appears if the counter contents equalsor exceeds said limit value; a fault-free simulation stage means for simulating fault-free operation of said logic circuit driven in common with said simulation stage means, and having an output; and a multiplexer including a first input connected to said output of said counter, a second input connected to said output of said output stage means, a third input connected to said output of said fault-free simulation stage means, and an output, said multiplexer normally conducting the output of the output stage means to said multiplexer output and operable in response to said switching signal to conduct the output of the fault-free simulation stage means to said multiplexer output.

Claim 8

A stimulation model for simulating a stuck-open fault in a logic circuit which comprises field effect transistors, and in which output bit patterns are derived from a sequence of input bit patterns respectively applied in successive clock periods to the simulation model containing the stuck-open fault, the output bit patterns being compared to reference patterns valid for fault-free operation of said logic circuit, said model comprising: a simulation stage means for simulating the stuck-open fault in said logic circuit; an output stage means connected to said simulation stage for simulating a logic circuit affected by the stuck-open fault, said simulation stage means including first and second outputs connected to said output stage means and said output stage means including an output, sad output stage including means responsive to a signal appearing at said first output of said simulation stage which is not influenced by the stuck-open fault for through-connecting said signal to said output of said output stage means and responsive to a signal at said first output of said simulation stage which is influenced by the stuck-open fault through-connecting a preceding signal not influenced by said stuck-open fault which has appeared immediately therebefore; a detector means connected to said first and second outputs of said simulation stage means for producing an output signal in response to a signal at said first and second outputs indicating a stuck-open fault; a resettable counter connected to said detector means and including a clock input for receiving clock pulses corresponding to said clock periods, said resettable counter being enable by the output signal of said detector means to add clock pulses received via the clock input; a comparator including a first input connected to said counter to receive the counter contents and a second input for receiving a limit value corresponding to a maximum persistence time of said output signal in successive clock periods to be compared in said comparator to the counter contents, and an output at which a switching signal appears if the counter contents equalsor exceeds said limit value; a fault-free simulation stage means for simulating fault-free operation of said logic circuit driven in common with said simulation stage means, and having an output; and a multiplexer including a first input connected to said output of said counter, a second input connected to said output of said output stage means, a third input connected to said output of said fault-free simulation stage means, and an output, said multiplexer normally conducting the output of the output stage means to said multiplexer output and operable in response to said switching signal to conduct the output of the fault-free simulation stage means to said multiplexer output.

Claim 9

The simulation model of claim 6, wherein: said simulation stage means includes said fault-free simulation stage means; said output stage means has a data input connected to said stimulation stage means, and a control input; said fault-free simulation stage means in s drive stage driven in parallel with said simulation stage means and includes an output connected to said control input of said output stage means, said drive stage producing a first output signal in response to a signal at the inputs of said simulation stage means which is not influenced by the stuck-open fault and causing through-connection of said producing a second output signal in response to a signal input to said simulation stage means at the output of said output stage means; and a connection between said output of said drive stage and said resettable counter for initiating the adding in said counter of the clock pulses received via said clock input.

Claim 10

The simulation model of claim 7, further comprising: an AND gate connected between said detector means said resettable counter and including a first input connected to said detector means and a second input connected to the output of said multiplexer.

Claim 11

The simulation model of claim 8, and further comprising: an inverter connected to said first input of said AND gate, and a reset input for said resettable counter connected to said inverter.

Claim 12

The simulation model of claim 9, wherein: said multiplexer includes a further inverter and second and third AND gates each including a first input, a second input and an output, said first inputs connected together via said further inverter, said second input of said second AND gate connected to said output stage means and said second input of said third AND gate connected to said fault-free simulation stage means; and a logic circuit connected to said outputs of said second and third AND gates and connected to drive said counter.

Claim 13

The simulation model of claim 10, wherein: said logic circuit comprises an OR gate including first and second inputs respectively connected to said outputs of said second and third AND gates.

Claim 14

The simulation model of claim 11, wherein: said simulation stage means includes means operable for performing a NAND function and comprises a first NAND gate and a fourth AND gate, each of said gates including first and second together and said second inputs connected together and each of said commonly connected inputs connected to said logic circuit; and an RS flip-flop forming said output stage means and including an S input and an R input, said S input connected to said output of said NAND gate and said R input connected to said output of said AND gate.

Claim 15

The simulation model of claim 11, wherein: said counter comprises a D flip-flop including a D input and a Q output; said D input connected to said detector means; and a NAND gate including a first input connected to said Q output, a second input connected to said detector means and an output connected to said multiplexer.