CMOS RAM with merged bipolar transistor

Claim 1

An integrated circuit memory cell comprising, a substrate of a first conductivity type semiconductor material; a region of a second conductivity type semiconductor material located in said substrate and forming a well therein having a surface; six regions of said first conductivity type semiconductor material located in said well and forming six pockets therein arranged in two sets of three pockets each, the first and third pocket of each set being separated from the second along the surface of said well by sections of said well material comprising four in number; a thin oxide layer located on said four sections of said well material forming insulator layers; gate electrodes located on said four insulator layers; said gate electrodes and said six pockets comprising four field effect transistors, namely two data storage transistors and two drive transistors; one pocket in each set having a region of said second conductivity type semiconductor material located in it, each said region in a pocket comprising the emitter of a bipolar transistor with the pocket it is located in comprising the base and said well comprising the collector of said associated bipolar transistor.