US4868482A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS integrated circuit having precision resistor elements
Assignee: Western Digital Corp
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Filing: 1987-10-05
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Granted: 1989-09-19
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Expires: 2007-10-05
Abstract
Abstract A circuit is provided for realizing multiple precision resistor elements on an integrated circuit by sensing a reference resistor. The circuit contains a first current source which passes a first current through a reference resistor located either on or off of the integrated circuit to generate a reference voltage. The reference voltage is applied to the inverting input of a precision high gain operational amplifier. A second current source is connected to the drain of a first MOS transistor operating in its ohmic region. The second current source is also connected to the non-inverting input of the high gain operational amplifier. The output of the operational amplifier is electrically connected to the gate of the first and second MOS transistors. In operation, a precision resistance is developed across the second MOS transistor which is equal to or some determinable multiple of the resistance of the reference precision resistor located on or off chip. An operational amplifier adaptable to this circuit is also disclosed.
Inventors
- 👤 Timothy G. O'Shaughnessy
- 👤 Michael R. Spaur
- 👤 Kenneth W. Ouyang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 01:51
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/34; H03F3/343; H03F3/345; H03H; H03H11/00; H03H11/46
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
177 words
A circuit for providing a precision resistor on an integrated circuit, comprising: a reference resistor; a first current source connected to pass a first current through said reference resistor to establish a reference voltage; an operational amplifier having an inverting input, a non-inverting input, and an output, said reference voltage being applied to said inverting input of said operational amplifier; a MOS transistor having a gate, a source, and a drain, the output of said operational amplifier driving the gate of said MOS transistor; a second current source connected to pass a second current to said drain of said MOS transistor and to the non-inverting input of said operational amplifier, wherein the operational amplifier will drive the transistor so that its drain voltage is substantially equal to the reference voltage, thereby causing the transistor to have a constant resistance having a predetermined relationship to the resistance of the reference resistor; and at least one additional MOS transistor having its gate driven by the output of the operational amplifier, each additional transistor providing a resistance of predetermined value.
Claim 2
Dependent Claim
177 words
A circuit for providing a precision resistor on an integrated circuit, comprising: a reference resistor; a first current source connected to pass a first current through said reference resistor to establish a reference voltage; an operational amplifier having an inverting input, a non-inverting input, and an output, said reference voltage being applied to said inverting input of said operational amplifier; a MOS transistor having a gate, a source, and a drain, the output of said operational amplifier driving the gate of said MOS transistor; a second current source connected to pass a second current to said drain of said MOS transistor and to the non-inverting input of said operational amplifier, wherein the operational amplifier will drive the transistor so that its drain voltage is substantially equal to the reference voltage, thereby causing the transistor to have a constant resistance having a predetermined relationship to the resistance of the reference resistor; and at least one additional MOS transistor having its gate driven by the output of the operational amplifier, each additional transistor providing a resistance of predetermined value.
Claim 3
Dependent Claim
16 words
A circuit according to claim 1, wherein said reference resistor is located on said integrated circuit.
Claim 4
Dependent Claim
17 words
A circuit according to claim 1, wherein said reference resistor is located off of said integrated circuit.
Claim 5
Dependent Claim
146 words
A circuit for providing a precision resistor on an integrated circuit, comprising: means for providing a reference voltage of predetermined value; an operational amplifier having an inverting input, a non-inverting input, and an output, said reference voltage being applied to said inverting input of said operational amplifier; a MOS transistor located on said integrated circuit, said MOS transistor having a gate, a source, and a drain, said output of said operational amplifier being electrically connected to said gate of said MOS transistor so as to maintain said MOS transistor at a fixed resistance and wherein said MOS transistor operates in the ohmic region; a current source passing a current of predetermined value to said drain of said MOS transistor and said non-inverting input of said operational amplifier; and at least one additional MOS transistor having its gate electrically connected to the output of the operational amplifier.
Claim 6
Dependent Claim
146 words
A circuit for providing a precision resistor on an integrated circuit, comprising: means for providing a reference voltage of predetermined value; an operational amplifier having an inverting input, a non-inverting input, and an output, said reference voltage being applied to said inverting input of said operational amplifier; a MOS transistor located on said integrated circuit, said MOS transistor having a gate, a source, and a drain, said output of said operational amplifier being electrically connected to said gate of said MOS transistor so as to maintain said MOS transistor at a fixed resistance and wherein said MOS transistor operates in the ohmic region; a current source passing a current of predetermined value to said drain of said MOS transistor and said non-inverting input of said operational amplifier; and at least one additional MOS transistor having its gate electrically connected to the output of the operational amplifier.
Claim 7
Dependent Claim
43 words
A circuit according to claim, 4, wherein said means for providing a reference voltage of predetermined value comprises: a reference resistor of predetermined resistance; and a second current source having a second current of predetermined value which is applied to said reference resistor.
Claim 8
Dependent Claim
24 words
A circuit according to claim 1, or 4, wherein said operational amplifier provides no more than two states of inversion through its non-inverting input.
Claim 9
Dependent Claim
17 words
A circuit according to claim 6, wherein said operational amplifier includes a single ended differential input stage.
Claim 10
Dependent Claim
29 words
A circuit according to claim 4, further comprising a resistor connected between the output of the operational amplifier and the gate of said at least one additional MOS transistor.
Claim 11
Dependent Claim
74 words
A circuit according to claim 8, further comprising means for providing a reference potential, wherein the resistor comprises a supplemental MOS transistor having a gate, a source and a drain, the supplemental MOS transistor having its gate connected to the reference potential to render the supplemental MOS transistor conductive, its source connected to the output of the operational amplifier, and its drain connected to the gate of said at least one additional MOS transistor.
Claim 12
Dependent Claim
138 words
A circuit for providing a precision resistor on an integrated circuit, comprising: a first MOS transistor operating in the ohmic region; means for providing a current of predetermined value to the first MOS transistor to establish a first voltage across the first MOS transistor; means for providing a reference voltage; biasing means, coupled to the first MOS transistor and the means for providing a reference voltage, for biasing the first voltage across the first MOS transistor to be equal to the reference voltage, thereby causing the first MOS transistor to have a resistance equal to the ratio of the reference voltage over the current of predetermined value; and at least one additional MOS transistor biased by the biasing means in a manner identical to the first MOS transistor, each additional MOS transistor having a resistance of predetermined value.
Claim 13
Dependent Claim
138 words
A circuit for providing a precision resistor on an integrated circuit, comprising: a first MOS transistor operating in the ohmic region; means for providing a current of predetermined value to the first MOS transistor to establish a first voltage across the first MOS transistor; means for providing a reference voltage; biasing means, coupled to the first MOS transistor and the means for providing a reference voltage, for biasing the first voltage across the first MOS transistor to be equal to the reference voltage, thereby causing the first MOS transistor to have a resistance equal to the ratio of the reference voltage over the current of predetermined value; and at least one additional MOS transistor biased by the biasing means in a manner identical to the first MOS transistor, each additional MOS transistor having a resistance of predetermined value.
Claim 14
Independent Claim
210 words
A method of driving an MOS transistor to provide a precision resistance, comprising the steps of: providing an integrated circuit, a reference precision resistor element having a predetermined value of resistance, a first current of predetermined value, providing a first MOS transistor on the integrated circuit, the first MOS transistor operating in the ohmic region and having a value of resistance which is related to the voltage applied to its gate as well as other variable parameters; passing the first current through the reference precision resistor to establish a reference voltage; passing the second current through the first MOS transistor to establish a transistor drain to source voltage across the MOS transistor; biasing the transistor drain to source voltage to be equal to the reference voltage, thereby maintaining the resistance of the first MOS transistor at a constant value irrespective of variations in said other variable parameters, said constant value being substantially equal to the resistance of the reference precision resistor element multiplied by the ratio of the first current of predetermined value over the second current of predetermined value; providing at least one additional MOS transistor; and biasing each additional MOS transistor to have a resistance which is a determinable multiple of the resistance of the first MOS transistor.
Claim 15
Independent Claim
210 words
A method of driving an MOS transistor to provide a precision resistance, comprising the steps of: providing an integrated circuit, a reference precision resistor element having a predetermined value of resistance, a first current of predetermined value, providing a first MOS transistor on the integrated circuit, the first MOS transistor operating in the ohmic region and having a value of resistance which is related to the voltage applied to its gate as well as other variable parameters; passing the first current through the reference precision resistor to establish a reference voltage; passing the second current through the first MOS transistor to establish a transistor drain to source voltage across the MOS transistor; biasing the transistor drain to source voltage to be equal to the reference voltage, thereby maintaining the resistance of the first MOS transistor at a constant value irrespective of variations in said other variable parameters, said constant value being substantially equal to the resistance of the reference precision resistor element multiplied by the ratio of the first current of predetermined value over the second current of predetermined value; providing at least one additional MOS transistor; and biasing each additional MOS transistor to have a resistance which is a determinable multiple of the resistance of the first MOS transistor.
Claim 16
Independent Claim
167 words
A method of providing a precision reference resistor on an integrated circuit, comprising the steps of: providing an integrated circuit, a reference precision voltage of predetermined value, and a current of predetermined value; providing a first MOS transistor on the integrated circuit, the first MOS transistor operating in the ohmic region and having a gate, a drain and a source and a value of resistance which is related to the voltage applied to the gate; passing the current of known value through the first MOS transistor to establish a drain to source voltage; biasing the transistor drain to source voltage to be substantially equal to the reference precision voltage, thereby adjusting the resistance of the first MOS transistor to a constant value equal to the ratio of the reference precision voltage to the current of predetermined value; providing at least one additional MOS transistor; and biasing each additional MOS transistor to have a resistance which is a determinable multiple of the resistance of the first MOS transistor.
Claim 17
Independent Claim
167 words
A method of providing a precision reference resistor on an integrated circuit, comprising the steps of: providing an integrated circuit, a reference precision voltage of predetermined value, and a current of predetermined value; providing a first MOS transistor on the integrated circuit, the first MOS transistor operating in the ohmic region and having a gate, a drain and a source and a value of resistance which is related to the voltage applied to the gate; passing the current of known value through the first MOS transistor to establish a drain to source voltage; biasing the transistor drain to source voltage to be substantially equal to the reference precision voltage, thereby adjusting the resistance of the first MOS transistor to a constant value equal to the ratio of the reference precision voltage to the current of predetermined value; providing at least one additional MOS transistor; and biasing each additional MOS transistor to have a resistance which is a determinable multiple of the resistance of the first MOS transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-18 | 1993-03-20 | 1993-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-18 | 1997-03-20 | 1997-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-18 | 2001-03-20 | 2001-09-19 | $7700.00 | Window Closed / Lapsed |