US4868422A
Expired / Lapsed
US
⏱️ 0.0 years remaining
TTL compatible CMOS logic circuit for driving heavy capacitive loads at high speed
Assignee: STMicroelectronics SRL
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Filing: 1987-12-09
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Granted: 1989-09-19
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Expires: 2007-12-09
Abstract
Abstract CMOS logic circuit with one or more inputs has at least a complementary pair of transistors, the N-channel driver transistor having a gate directly connected to an input while the P-channel load transistor having a gate connected to the output of the second one of two inverters connected in cascade, the input of the first inverter being connected to the input of the circuit. Using two signal inverting stages or inverters for mirroring the input signal on the gate of the load P-channel transistor of the circuit pair permits the defining of the triggering threshold of the circuit with great freedom, the obtaining of a greater switching speed and the reduction of power dissipation under stand-by conditions. The invention is particularly suited for HCT circuits.
Inventors
- 👤 Vincenzo Daniele
- 👤 Mirella Benedetti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:39
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948; H03K19/0005; H03K19/01; H03K19/017; H03K19/01707
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
186 words
A CMOS logic circuit comprising: at least one N-channel transistor having a gate connected to an input, a source connected to a first common potential (V SS ) and a drain connected, either directly or through one or more other N-channel transistors having their respective gates connected to a corresponding number of inputs, to an output node; and at least one P-channel transistor having a source connected to a second common potential (V DD ), a drain connected, either directly or through one or more P-channel transistors to said output node; wherein the gate of said P-channel transistor is connected to the output of the second of two cascade-connected auxiliary signal inverting stages, the first of which being an inverter which determines a triggering threshold voltage of the circuit and the second of which being a logic gate whose output level depends from the state of the output of said inverter; the input of said inverter being connected to said input node of the circuit; and the input of the second of said two auxiliary signal inverting stages being connected to the output of said inverter.
Claim 2
Dependent Claim
186 words
A CMOS logic circuit comprising: at least one N-channel transistor having a gate connected to an input, a source connected to a first common potential (V SS ) and a drain connected, either directly or through one or more other N-channel transistors having their respective gates connected to a corresponding number of inputs, to an output node; and at least one P-channel transistor having a source connected to a second common potential (V DD ), a drain connected, either directly or through one or more P-channel transistors to said output node; wherein the gate of said P-channel transistor is connected to the output of the second of two cascade-connected auxiliary signal inverting stages, the first of which being an inverter which determines a triggering threshold voltage of the circuit and the second of which being a logic gate whose output level depends from the state of the output of said inverter; the input of said inverter being connected to said input node of the circuit; and the input of the second of said two auxiliary signal inverting stages being connected to the output of said inverter.
Claim 3
Dependent Claim
140 words
The circuit according to claim 1, wherein the circuit is a NAND circuit having said at least one P-channel transistor connected in parallel to at least another P-channel transistor and said at least one N-channel transistor series connected to another N-channel transistor and at least two other cascade-connected auxiliary inverting stages to form two sets of two cascade-connected auxiliary inverting stages, the input of each of the first of the two cascade-connected auxiliary inverting stages of said two sets of two cascade-connected auxiliary inverting stages being connected to a corresponding input and the gate of a corresponding one of the N-channel transistors, and the output of each of the second of the two cascade-connected auxiliary inverting stages of said two sets of two cascade-connected auxiliary inverting stages being connected to the gate of a corresponding one of the P-channel transistors.
Claim 4
Dependent Claim
140 words
The circuit according to claim 1, wherein the circuit is a NOR circuit having said at least one P-channel transistor connected in series to another P-channel transistor and said at least one N-channel transistor connected in parallel to another N-channel transistor and at least two other cascade-connected auxiliary inverting stages to form two sets of two cascade-connected auxiliary inverting stages, the input of each of the first of the two cascade-connected auxiliary inverting stages of said two sets of two cascade-connected auxiliary inverting stages being connected to a corresponding input and the gate of a corresponding one of the N-channel transistors, and the output of each of the second of the two cascade-connected auxiliary stages of said two sets of two cascade-connected auxilliary inverting stages being connected to the gate of a corresponding one of the series connected P-channel transistor.
Claim 5
Dependent Claim
134 words
A CMOS input stage comprising: a CMOS inverting stage having an input terminal and an output terminal, formed by an N-channel transistor and a P-channel transistor with source-drain paths functionally connected in series between a positive voltage supply rail and ground; said transistors being respectively dimensioned to sink and source current to said output terminal for driving at a high speed a capacitive load connected thereto, wherein said N-channel transistor has a gate connected to said input terminal; said P-channel transistor has a gate connected to an output of the second of two cascaded auxiliary CMOS inverters, the input of the first of said two cascaded auxiliary CMOS inverters being connected to said input terminal; said auxiliary CMOS inverters being formed with transistors having substantially smaller dimensions than both said N-channel and P-channel transistors.
Claim 6
Dependent Claim
134 words
A CMOS input stage comprising: a CMOS inverting stage having an input terminal and an output terminal, formed by an N-channel transistor and a P-channel transistor with source-drain paths functionally connected in series between a positive voltage supply rail and ground; said transistors being respectively dimensioned to sink and source current to said output terminal for driving at a high speed a capacitive load connected thereto, wherein said N-channel transistor has a gate connected to said input terminal; said P-channel transistor has a gate connected to an output of the second of two cascaded auxiliary CMOS inverters, the input of the first of said two cascaded auxiliary CMOS inverters being connected to said input terminal; said auxiliary CMOS inverters being formed with transistors having substantially smaller dimensions than both said N-channel and P-channel transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-18 | 1993-03-20 | 1993-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-18 | 1997-03-20 | 1997-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-18 | 2001-03-20 | 2001-09-19 | $7700.00 | Window Closed / Lapsed |