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US4868414A
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Scan-path self-testing circuit for logic units
Assignee: NEC Corp
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Filing: 1988-02-26
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Granted: 1989-09-19
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Expires: 2008-02-26
Abstract
Abstract For a plurality of logic units which are organized into scan-path groups, a scan-path self-testing circuit is provided which comprises a clock source and a plurality of gates for supplying the clock pulse to the logic units when selectively enabled. To give flexibility to group organization of the logic units, the gates are provided in a one-to-one relationship with the logic units. Bit positions of a register are associated respectively with the gates. A scan path controller selects one of the scan-path groups and writes a logic 1 into the register bit positions which are associated with the logic units of the selected scan-path group.
Inventors
- 👤 Takashi Kanazawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:27
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318536
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
147 words
A scan-path self-testing circuit comprising: a scan-path controller for generating gate selection bits and having a plurality of scan-path input terminals, a scan-path output terminal, and a plurality of gate selection terminals at which said gate selection bits appear respectively; a plurality of groups of logic units, the logic units of each group being connected in series from said scan-path output terminal to one of said scan-path input terminals; a clock source for generating a clock pulse; a register having a plurality of stages respectively connected to said gate selection terminals of said scan-path controller; and a plurality of clock gates having first input terminals connected together to said clock source, second input terminals connected respectively to said stages of said register and output terminals connected respectively to clock inputs of said logic units for supplying said clock pulse thereto in response to said gate selection bits.
Claim 2
Dependent Claim
147 words
A scan-path self-testing circuit comprising: a scan-path controller for generating gate selection bits and having a plurality of scan-path input terminals, a scan-path output terminal, and a plurality of gate selection terminals at which said gate selection bits appear respectively; a plurality of groups of logic units, the logic units of each group being connected in series from said scan-path output terminal to one of said scan-path input terminals; a clock source for generating a clock pulse; a register having a plurality of stages respectively connected to said gate selection terminals of said scan-path controller; and a plurality of clock gates having first input terminals connected together to said clock source, second input terminals connected respectively to said stages of said register and output terminals connected respectively to clock inputs of said logic units for supplying said clock pulse thereto in response to said gate selection bits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-18 | 1993-03-20 | 1993-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-18 | 1997-03-20 | 1997-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-18 | 2001-03-20 | 2001-09-19 | $7700.00 | Window Closed / Lapsed |