Patent US4868413A successfully refreshed from Google Patents.
US4868413A
Expired / Lapsed
US
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Testable passgate logic circuits
Assignee: International Business Machines Corp
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Filing: 1988-04-20
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Granted: 1989-09-19
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Expires: 2008-04-20
Abstract
Abstract A logic circuit is provided which includes a multiplexer having a plurality of parallelly arranged channels, each channel including a switching device having a control element and responsive to a first control signal, a plurality of signal terminals, a common terminal, each of the channels being connected between a respective one of the plurality of signal terminals and the common terminal, and a termination circuit which includes a series circuit having a plurality of switching devices, each having a control element and being responsive to a second control signal. The control elements of each of the plurality of switching devices of the series circuit are coupled to a respective one of the control elements of the switching devices of the channels so that when one of the switching devices of the series circuit is turned on, the respective one of the switching devices of the channels is turned off, and vice versa.
Inventors
- 👤 Steven F. Oakland
- 👤 Clarence R. Ogilvie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:02
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/693
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
180 words
A logic circuit comprising a data source having first and second output terminals, a common output terminal, a switching network including a first channel having a first switching device and a second channel having a second switching device, each of said switching devices having a control element, said first channel being connected between the first output terminal of said data source and said common output terminal and said second channel being connected between the second output terminal of said data source and said common output terminal, a control source having first and second output terminals, an output termination circuit having third and fourth serially-arranged switching devices, each having a control element, connected between said common output terminal and a point of reference potential, and means coupling the first and second output terminals of said control source to the control elements of said first, second, third and fourth switching devices for simultaneously turning on said first switching device and turning off said third switching device and for simultaneously turning of said second switching device and turning on said fourth switching device.
Claim 2
Dependent Claim
180 words
A logic circuit comprising a data source having first and second output terminals, a common output terminal, a switching network including a first channel having a first switching device and a second channel having a second switching device, each of said switching devices having a control element, said first channel being connected between the first output terminal of said data source and said common output terminal and said second channel being connected between the second output terminal of said data source and said common output terminal, a control source having first and second output terminals, an output termination circuit having third and fourth serially-arranged switching devices, each having a control element, connected between said common output terminal and a point of reference potential, and means coupling the first and second output terminals of said control source to the control elements of said first, second, third and fourth switching devices for simultaneously turning on said first switching device and turning off said third switching device and for simultaneously turning of said second switching device and turning on said fourth switching device.
Claim 3
Dependent Claim
84 words
A logic circuit as set forth in claim 1 wherein said first and second switching devices are N channel field effect transistors and said third and fourth switching devices are P channel field effect transistors and said means includes a direct connection from the first output terminal of said control source to the control elements of said first and third transistors and a direct connection from the second output terminal of said control source to the control elements of said second and fourth transistors.
Claim 4
Dependent Claim
20 words
A logic circuit as set forth in claim 2 further including a capacitive load connected to said common output terminal.
Claim 5
Dependent Claim
168 words
A logic circuit comprising a data source having a given plurality of output terminals, a common output terminal, a capacitor connected to said common output terminal, a multiplexer including a given plurality of data channels, each of said channels having a transistor, including a gate electrode, connected between a different one of said given plurality of output terminals of said data source and said common output terminal, a control source having a given plurality of output terminals, an output termination circuit having a given plurality of serially-arranged transistors, each of said serially-arranged transistors including a gate electrode, the gate electrodes of each of said given plurality of serially-arranged transistors being coupled to a respective one of the gate electrodes of said transistors of said multiplexer, and means coupling the given plurality of output terminals of said control source to respective gate electrodes of said serially-arranged transistors for selectively turning off each of the serially-arranged transistors and simultaneously turning on its respective one of said transistors of said multiplexer.
Claim 6
Dependent Claim
168 words
A logic circuit comprising a data source having a given plurality of output terminals, a common output terminal, a capacitor connected to said common output terminal, a multiplexer including a given plurality of data channels, each of said channels having a transistor, including a gate electrode, connected between a different one of said given plurality of output terminals of said data source and said common output terminal, a control source having a given plurality of output terminals, an output termination circuit having a given plurality of serially-arranged transistors, each of said serially-arranged transistors including a gate electrode, the gate electrodes of each of said given plurality of serially-arranged transistors being coupled to a respective one of the gate electrodes of said transistors of said multiplexer, and means coupling the given plurality of output terminals of said control source to respective gate electrodes of said serially-arranged transistors for selectively turning off each of the serially-arranged transistors and simultaneously turning on its respective one of said transistors of said multiplexer.
Claim 7
Dependent Claim
19 words
A logic circuit as set forth in claim 4 wherein each of said transistors is a field effect transistor.
Claim 8
Dependent Claim
40 words
A logic circuit as set forth in claim 5 wherein each of the transistors of said multiplexer is an N channel field effect transistor and each of the transistors of said termination circuit is a P channel field effect transistor.
Claim 9
Dependent Claim
52 words
A logic circuit as set forth in claim 6 wherein the gate electrodes of each of said given plurality of serially-arranged transistors are directly connect to a respective one of the gate electrodes of said transistors of said multiplexer and to a respective one of the output terminals of said control source.
Claim 10
Dependent Claim
130 words
A logic circuit comprising a given plurality of data source terminals, a common output terminal, a given plurality of data channels, each channel being connected between a respective one of said given plurality of data source terminals and said common output terminal and each channel including a transistor having a control element, a point of reference potential, a given plurality of serially-arranged transistors, each having a control element, coupled between said common output terminal and said point of reference potential, a given plurality of control source terminals, and means coupling said given plurality of control source terminals to the control elements of said transistors for selectively turning off each of said serially-connected transistors and turning on a respective one of a said transistors of said given plurality of data channels.
Claim 11
Dependent Claim
130 words
A logic circuit comprising a given plurality of data source terminals, a common output terminal, a given plurality of data channels, each channel being connected between a respective one of said given plurality of data source terminals and said common output terminal and each channel including a transistor having a control element, a point of reference potential, a given plurality of serially-arranged transistors, each having a control element, coupled between said common output terminal and said point of reference potential, a given plurality of control source terminals, and means coupling said given plurality of control source terminals to the control elements of said transistors for selectively turning off each of said serially-connected transistors and turning on a respective one of a said transistors of said given plurality of data channels.
Claim 12
Dependent Claim
19 words
A logic circuit as set forth in claim 8 wherein each of said transistors is a field effect transistor.
Claim 13
Dependent Claim
45 words
A logic circuit as set forth in claim 9 wherein each of the transistors of said given plurality of data channels is an N channel field effect transistor and each of the transistors of said given plurality of serially-connected transistors is a P channel transistor.
Claim 14
Dependent Claim
31 words
A logic circuit as set forth in claim 10 wherein said means includes direct electrical connections from said given plurality of control source terminals to the control elements of said transistors.
Claim 15
Dependent Claim
166 words
A logic circuit comprising a data source having first and second output terminals, a common output terminal, a capacitor connected between said common output terminal and a point of reference potential, a first transistor connected between the first output terminal of said data source and said common output terminal, a second transistor connected between the second output terminal of said data source and said common output terminal, a voltage source, third and fourth transistors serially connected between said common output terminal and said voltage source, said first and second transistors being of a given conductivity type and said third and fourth transistors being of a conductivity type opposite to that of the given conductivity type, and a control source having first and second output terminals, the first output terminal of said control source being connected to the control elements of said first and third transistors and the second output terminal of said control source being connected to the control elements of said second and fourth transistors.
Claim 16
Dependent Claim
166 words
A logic circuit comprising a data source having first and second output terminals, a common output terminal, a capacitor connected between said common output terminal and a point of reference potential, a first transistor connected between the first output terminal of said data source and said common output terminal, a second transistor connected between the second output terminal of said data source and said common output terminal, a voltage source, third and fourth transistors serially connected between said common output terminal and said voltage source, said first and second transistors being of a given conductivity type and said third and fourth transistors being of a conductivity type opposite to that of the given conductivity type, and a control source having first and second output terminals, the first output terminal of said control source being connected to the control elements of said first and third transistors and the second output terminal of said control source being connected to the control elements of said second and fourth transistors.
Claim 17
Dependent Claim
16 words
A logic circuit as set forth in claim 12 wherein said transistors are field effect transistors.
Claim 18
Dependent Claim
37 words
A logic circuit as set forth in claim 13 wherein said first and second transistors of given conductivity type are N channel field effect transistors and said third and fourth transistors are P channel field effect transistors.
Claim 19
Dependent Claim
116 words
A circuit comprising first and second transistors arranged in parallel and connected to a common terminal, said first and second transistors being of a given conductivity type and having control elements, a series circuit including third and fourth transistors connected to the common terminal, said third and fourth transistors being of an opposite conductivity type to that of said given conductivity type and having control elements, means for applying a first predetermined control pulse to the control elements of said first and third transistors and a second predetermined control pulse to the control elements of said second and fourth transistor, and means for applying data signals through said first and second transistors to said common terminal.
Claim 20
Dependent Claim
116 words
A circuit comprising first and second transistors arranged in parallel and connected to a common terminal, said first and second transistors being of a given conductivity type and having control elements, a series circuit including third and fourth transistors connected to the common terminal, said third and fourth transistors being of an opposite conductivity type to that of said given conductivity type and having control elements, means for applying a first predetermined control pulse to the control elements of said first and third transistors and a second predetermined control pulse to the control elements of said second and fourth transistor, and means for applying data signals through said first and second transistors to said common terminal.
Claim 21
Dependent Claim
33 words
A logic circuit as set forth in claim 15 wherein said first and second transistors are N channel field effect transistors and said third and fourth transistors are P channel field effect transistors.
Claim 22
Dependent Claim
119 words
A circuit comprising a switching network having a plurality of parallelly-arranged channels, each channel including a switching device having a control element and being responsive to a first signal from a control source, a plurality of signal terminals, a common terminal, each of said channels being connected between a respective one of said plurality of signal terminals and said common terminal, and a termination circuit including a series circuit having a plurality of switching devices, each having a control element and being responsive to a second signal from said control source, the control elements of each of said plurality of switching devices being coupled to a respective one of the control elements of the switching devices of said channels.
Claim 23
Dependent Claim
119 words
A circuit comprising a switching network having a plurality of parallelly-arranged channels, each channel including a switching device having a control element and being responsive to a first signal from a control source, a plurality of signal terminals, a common terminal, each of said channels being connected between a respective one of said plurality of signal terminals and said common terminal, and a termination circuit including a series circuit having a plurality of switching devices, each having a control element and being responsive to a second signal from said control source, the control elements of each of said plurality of switching devices being coupled to a respective one of the control elements of the switching devices of said channels.
Claim 24
Dependent Claim
35 words
A circuit as set forth in claim 17 wherein the switching devices of said channels are N channel field effect transistors and the switching devices of said termination circuit are P channel field effect transistors.
Claim 25
Dependent Claim
135 words
A logic circuit as set forth in claim 1 wherein said means couples the first and second output terminals of said control source to the control elements of said first, second, third and fourth switching devices for simultaneously turning on said first switching device and turning of said third switching device and for simultaneously turning off said second switching device and turning on said fourth switching device during a first period of time and couples the first and second output terminals of said control source to the control elements of said first, second, third and fourth switching devices for simultaneously turning off said first switching device and turning on said third switching device and for simultaneously turning on said second switching device and turning off said fourth switching device during a second period of time.
Claim 26
Dependent Claim
16 words
A logic circuit as set forth in claim 4 wherein said means includes electrically conductive lines.
Claim 27
Dependent Claim
30 words
A circuit as set forth in claim 15 further including a point of reference potential, said series circuit being connected between said point of reference potential and said common terminal.
Claim 28
Dependent Claim
35 words
A circuit as set forth in claim 18 wherein said first signal has a voltage of a first magnitude and said second signal has a voltage of a second magnitude different from said first magnitude.
References Cited (Backward Citations)
US3397325A
Cited
US4280212A
Cited
US4356413A
Cited
US4551634A
Cited
US4567385A
Cited
US4524443A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-18 | 1993-03-20 | 1993-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-18 | 1997-03-20 | 1997-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-18 | 2001-03-20 | 2001-09-19 | $7700.00 | Window Closed / Lapsed |