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Method for manufacturing a Bi-CMOS device

Assignee: International Business Machines Corp
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Filing: 1988-12-21
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Granted: 1989-09-19
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Expires: 2008-12-21
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Abstract

Abstract A method for fabricating a Bi-CMOS device is disclosed herein, which device can include both vertical PNP and NPN components. The process steps include forming the reach-through N+ subcollector to the bipolar device without extra processing steps; combining into one mask the threshold adjust/well implants with self-aligned isolation leakage protection implants by using a self-aligned, removable oxide mask prior to field isolation; using a resist etch-back scheme to protect against emitter-to-base punch-through while self-aligning the pedestal and base; and also providing for the removal of the gate oxide at the emitter while maintaining it at the FET, without extra masks. The device incorporates similar structural featues between the bi-polar and FET devices. The NPN and pFET can share the same well and a P+ diffusion (the p+ extrinsic base is the same as the p+ source). Also, the pnp and nFET can share the same well and an n+ diffusion.

Inventors

  • 👤 Seiki Ogura
  • 👤 Nivo Rovedo

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 16:06
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10D84/403

Claims Analysis

Total Claims: 22
Claim 1
Independent Claim 368 words
In a process for the simultaneous production of vertical NPN and PNP bipolar transistors and complementary field effect transistors on a common P-doped epitaxial layer wherein said substrate has an epi layer grown on its surface and said substrate has formed at selected locations N+ subcollector areas which subcollectors are oxidized to a different height for alignment of subsequent masks and said substrate has also formed therein P+ subcollectors at selected locations for providing a low resistance path to the substrate, the improvement to the process comprising the steps of: (a) growing/depositing a thin oxide and nitride layer on the surface of said wafer and depositing an oxide layer onto said nitride layer, (b) patterning said oxide/nitride/oxide layer to locate the surface isolation areas, (c) masking said n well regions, (d) implanting n type dopant at the exposed regions to form a device guard ring, (e) removing the exposed oxide layer and implanting n type dopant to adjust the threshold voltage, (f) removing the n well resist mask and repeating steps c-e for the P well for the n/FET and PNP substituting P type dopant for the n-type dopant, and then removing the P well resist, (g) oxidizing the field, removing the nitride/pad oxide layer and growing a gate oxide, (h) blanket depositing a layer of LPCVD polysilicon, (i) masking said polysilicon with resist and selectively etching said polysilicon down to the gate oxide in the bipolar emitter region and collector reach-through region, (j) implanting an n-type pedestal collector in said opened locations, (k) etching back the photoresist, (1) implanting P type dopant into the bipolar base well, (m) removing the photoresist mask, (n) repeating steps g-m for the opposite type of bipolar device substituting P type dopant for the n type dopant, (o) removing the gate oxide layer, (p) depositing a second layer of polysilicon on the surface, (q) doping the polysilicon, (r) patterning the polysilicon to form the gate electrodes and polysilicon emitter contacts whereby a recess is produced at the surface adjacent to the emitter contact, and (s) forming the respective p type and n type reach-through, extrinsic base, and source and drain using photoresist masks and implanting the respective dopant in the predetermined regions.
Claim 2
Dependent Claim 368 words
In a process for the simultaneous production of vertical NPN and PNP bipolar transistors and complementary field effect transistors on a common P-doped epitaxial layer wherein said substrate has an epi layer grown on its surface and said substrate has formed at selected locations N+ subcollector areas which subcollectors are oxidized to a different height for alignment of subsequent masks and said substrate has also formed therein P+ subcollectors at selected locations for providing a low resistance path to the substrate, the improvement to the process comprising the steps of: (a) growing/depositing a thin oxide and nitride layer on the surface of said wafer and depositing an oxide layer onto said nitride layer, (b) patterning said oxide/nitride/oxide layer to locate the surface isolation areas, (c) masking said n well regions, (d) implanting n type dopant at the exposed regions to form a device guard ring, (e) removing the exposed oxide layer and implanting n type dopant to adjust the threshold voltage, (f) removing the n well resist mask and repeating steps c-e for the P well for the n/FET and PNP substituting P type dopant for the n-type dopant, and then removing the P well resist, (g) oxidizing the field, removing the nitride/pad oxide layer and growing a gate oxide, (h) blanket depositing a layer of LPCVD polysilicon, (i) masking said polysilicon with resist and selectively etching said polysilicon down to the gate oxide in the bipolar emitter region and collector reach-through region, (j) implanting an n-type pedestal collector in said opened locations, (k) etching back the photoresist, (1) implanting P type dopant into the bipolar base well, (m) removing the photoresist mask, (n) repeating steps g-m for the opposite type of bipolar device substituting P type dopant for the n type dopant, (o) removing the gate oxide layer, (p) depositing a second layer of polysilicon on the surface, (q) doping the polysilicon, (r) patterning the polysilicon to form the gate electrodes and polysilicon emitter contacts whereby a recess is produced at the surface adjacent to the emitter contact, and (s) forming the respective p type and n type reach-through, extrinsic base, and source and drain using photoresist masks and implanting the respective dopant in the predetermined regions.
Claim 3
Dependent Claim 21 words
A process according to claim 1 wherein said oxide/nitride/oxide layer are, respectively, approximately 250 Å, 1000 Å, and 5000 Å thick.
Claim 4
Dependent Claim 22 words
A process according to claim 2 wherein said guard ring has a dopant concentration of 10 -12 -10 -- cm -2 .
Claim 5
Dependent Claim 28 words
A process according to claim 3 wherein the field is oxidized to a thickness of approximately 5000 Å-6000 Å and the gate oxide is 100 Å-150 Å thick.
Claim 6
Dependent Claim 18 words
A process according to claim 4 wherein the blanket deposit of LPCVD polysilicon is 5000 Å-600 Å thick.
Claim 7
Dependent Claim 16 words
A process according to claim 5 wherein the polysilicon is selectively etched by reactive ion etching.
Claim 8
Dependent Claim 24 words
A process according to claim 6 wherein the polysilicon masking resist is etched backed either by a resist strip tool or directional RIE tool.
Claim 9
Dependent Claim 16 words
A process according to claim 7 wherein the gate oxide is removed by dilute hydrofluoric acid.
Claim 10
Dependent Claim 17 words
A process according to claim 8 wherein the second, thicker polysilicon deposition is 1500 Å-3000 Å thick.
Claim 11
Dependent Claim 27 words
A process according to claim 9 wherein onto the second layer of polysilicon is located a layer of a silicide followed by a layer of CVD oxide.
Claim 12
Dependent Claim 12 words
A process according to claim 10 wherein the silicide is tungsten silicide.
Claim 13
Dependent Claim 12 words
A process according to claim 10 wherein the silicide is titanium silicide.
Claim 14
Dependent Claim 23 words
A process according to claim 10 wherein the gate electrode stacks and emitter electrode stacks are patterned by selective removal of the polysilicon.
Claim 15
Dependent Claim 18 words
A process according to claim 13 wherein the selective removal of the polysilicon is by reactive ion etching.
Claim 16
Dependent Claim 23 words
A process according to claim 14 wherein an oxide spacer layer is formed at the edges of the emitter contact and gate contact.
Claim 17
Dependent Claim 15 words
A process according to claim 15 wherein the oxide layer is 300 Å-1000 Å thick.
Claim 18
Dependent Claim 33 words
A process according to claim 16 wherein two ion implants are made to form the P+ source/drain and extrinsic base of the PNP/PFET and the n+ source/drain and extrinsic base of the nFET/NPN.
Claim 19
Dependent Claim 39 words
A process according to claim 16 wherein a second oxide spacer layer is formed at the edges of the emitter contact and gate contact which can then be followed by ion implants to form the source/drain and base regions.
Claim 20
Dependent Claim 18 words
A process according to claim 1 wherein the P+ subcollector is isolated from the substrate by an oxide.
Claim 21
Dependent Claim 15 words
A process according to claim 19 wherein the oxide is formed by ion implantng oxygen.
Claim 22
Dependent Claim 23 words
A process according to claim 1 wherein the P+ subcollector is isolated from the substrate by use of an N type epitaxial layer.

References Cited (Backward Citations)

US4403395A Cited
US4553315A Cited
US4696092A Cited
US4778774A Cited
US4818719A Cited
US4784966A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-09-18 1993-03-20 1993-09-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-09-18 1997-03-20 1997-09-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-09-18 2001-03-20 2001-09-19 $7700.00 Window Closed / Lapsed

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