Memory control system using a single access request for doubleword data transfers from both odd and even memory banks

Claim 2

A memory access control system for a processor which generates a single access request, said system comprising: at least one main memory having a plurality of memory banks divided into two groups, bus means for transferring data and including a command/address bus line, a write data bus line, and a read data bus line all coupled to said main memory, and activating means, coupled to said bus means, for activating one access for one of said plurality of memory banks belonging to one group and another access for one of said plurality of memory banks belonging to the other group in response to the single access request allowing two data transfers, one from each group, to be sequentially performed on either the write data bus line or the read data bus line for the single access request transferred over the command/address bus line, said activating means comprising: detecting means for detecting that a single access request having a first address for one group is a double word access; means for generating a second address for the other group in response to detection of the double word access; and starting means for starting access in dependence on the first address and starting access in dependence on the second address.

Claim 3

A memory access control system for a processor which generates a single access request, said system comprising: at least one main memory having a plurality of memory banks divided into two groups, said two groups of said plurality of memory banks are constituted by memory banks having even numbers and memory banks having odd numbers, and each said even numbered memory bank adjoins a respective one of said odd numbered memory banks, bus means for transferring data and including a command/address bus line, a write data bus line, and a read data bus line all coupled to said main memory, and activating means, coupled to said bus means, for activating one access for one of said plurality of memory banks belonging to one group and another access for one of said plurality of memory banks belonging to the other group in dependence on the single access request allowing two sequential data transfers, one from each group, to be performed over said bus means for the single access request, said activating means comprising: detecting means for detecting that a single access request having a first address for one group is a double word access; means for generating a second address for the other group in response to detection of the double word access; and starting means for starting access in dependence on the first address and starting access in dependence on the second address.

Claim 4

A memory access control system for a processor which generates a single access request, said system comprising: at least one main memory having a plurality of memory banks divided into two groups, said two groups of said plurality of memory banks are constituted by memory banks having even numbers and memory banks having odd numbers, and each said even numbered memory bank adjoins a respective one of said odd numbered memory banks, bus means for transferring data and including a command/address bus line, a write data bus line, and a read data bus line all coupled to said main memory, and activating means, coupled to said bus means, for activating one access for one of said plurality of memory banks belonging to one group and another access for one of said plurality of memory banks belonging to the other group in dependence on the single access request allowing two sequential data transfers, one from each group, to be performed over said bus means for the single access request, said activating means comprising: detecting means for detecting that a single access request having a first address for one group is a double word access; means for generating a second address for the other group in response to detection of the double word access; and starting means for starting access in dependence on the first address and starting access in dependence on the second address.

Claim 5

A memory access control system as claimed in claim 1, wherein said activating means further comprises: a command/address register, connected to said command/address bus line, for sending two-word commands to said main memory and for designating an address for a selected memory bank of each of said two groups, a decoder, connected to said command/address register and said main memory, for activating each respective designated memory bank, a write data register, connected to said write data bus line, for transferring write data, and a read data register, connected to said read data bus line, for transferring read data.

Claim 6

A memory access control system, comprising: at least one main memory having a plurality of memory banks divided into two groups, bus means for transferring data and including a command/address bus line, a write a data bus line, and a read data bus line all coupled to said main memory, and activating means, coupled to said bus means, for, in response to a single access request, simultaneously activating one access for one of said plurality of memory banks belonging to one group and another access for one of said plurality of memory banks belonging to the other group, said activating means comprising: detecting means for detecting that a single access request having a first address for one group is a double word access; means for generating a second address for the other group in response to detection of the double word access; and starting means for starting access in dependence on the first address and starting access in dependence on the second address; a control pipeline register, coupled to said command/address bus line, for controlling an output timing of read data in accordance with the command address, a write data pipeline register, coupled to said write data bus line, for controlling a write timing of partial store data in accordance with the write data, and two selector means, each coupled to said main memory, a first selector means coupled to said main memory and said write data pipeline registers as data inputs and said control pipeline register as a control input and a second selector means coupled to said first selector as an input to receive write data as an input and to said main memory as an output, for merging said partial store data with said write data.

Claim 7

A memory access control system, comprising: at least one main memory having a plurality of memory banks divided into two groups, bus means for transferring data and including a command/address bus line, a write a data bus line, and a read data bus line all coupled to said main memory, and activating means, coupled to said bus means, for, in response to a single access request, simultaneously activating one access for one of said plurality of memory banks belonging to one group and another access for one of said plurality of memory banks belonging to the other group, said activating means comprising: detecting means for detecting that a single access request having a first address for one group is a double word access; means for generating a second address for the other group in response to detection of the double word access; and starting means for starting access in dependence on the first address and starting access in dependence on the second address; a control pipeline register, coupled to said command/address bus line, for controlling an output timing of read data in accordance with the command address, a write data pipeline register, coupled to said write data bus line, for controlling a write timing of partial store data in accordance with the write data, and two selector means, each coupled to said main memory, a first selector means coupled to said main memory and said write data pipeline registers as data inputs and said control pipeline register as a control input and a second selector means coupled to said first selector as an input to receive write data as an input and to said main memory as an output, for merging said partial store data with said write data.

Claim 8

A memory access control system as claimed in claim 3, wherein said activating means further comprises a plurality of bank registers corresponding to said plurality of memory banks, each of said bank registers having an address register, a write data register, and a read data register.

Claim 9

A memory access control system for a processor which generates a single access request, said system comprising: at least one main memory having even and odd numbered memory banks divided into two groups, bus means for transferring data and including a command/address bus line, a write data bus line, and a read data bus line all coupled to said main memory, and activating means, coupled to said bus means, for activating one access for one of said plurality of memory banks belonging to one group and another access for one of said plurality of memory banks belonging to the other group in dependence on the single access request allowing two sequential data transfers, one from each group, to be performed over said bus means for the single access request, said activating means comprising: a command/address register, connected to said command/address bus line, for sending two-word commands to said main memory and for designating an address for a selected memory bank of each of said two groups, a decoder, connected to said command/address register and said main memory, for activating each respective designated memory bank, a write data register, connected to said write data bus line, for transferring write data, a read data register, connected to said read data bus line, for transferring read data, and a plurality of bank registers, corresponding to said plurality of memory banks, each of said bank registers having an address register, a write data register, and a read data register, each said even numbered memory bank and the respective adjoining odd numbered memory bank are simultaneously accessed by said address register responsive to said two-word command, and said even numbered memory bank stores data at the same timing of said access, and said odd numbered memory bank stores data after a delay of one cycle compared with the storing by said even numbered memory bank.

Claim 10

A memory access control system for a processor which generates a single access request, said system comprising: at least one main memory having even and odd numbered memory banks divided into two groups, bus means for transferring data and including a command/address bus line, a write data bus line, and a read data bus line all coupled to said main memory, and activating means, coupled to said bus means, for activating one access for one of said plurality of memory banks belonging to one group and another access for one of said plurality of memory banks belonging to the other group in dependence on the single access request allowing two sequential data transfers, one from each group, to be performed over said bus means for the single access request, said activating means comprising: a command/address register, connected to said command/address bus line, for sending two-word commands to said main memory and for designating an address for a selected memory bank of each of said two groups, a decoder, connected to said command/address register and said main memory, for activating each respective designated memory bank, a write data register, connected to said write data bus line, for transferring write data, a read data register, connected to said read data bus line, for transferring read data, and a plurality of bank registers, corresponding to said plurality of memory banks, each of said bank registers having an address register, a write data register, and a read data register, each said even numbered memory bank and the respective adjoining odd numbered memory bank are simultaneously accessed by said address register responsive to said two-word command, and said even numbered memory bank stores data at the same timing of said access, and said odd numbered memory bank stores data after a delay of one cycle compared with the storing by said even numbered memory bank.

Claim 11

A memory access control system as claimed in claim 4, wherein the memory banks have even and odd numbered banks and said activating means further comprises: a command/address register, connected to said command/address bus line, for sending two-word commands and for designating an address of a selected memory bank, a decoder, connected to said command/address register and said main memory, for activating the respective designated memory bank, a plurality of bank registers coupled to said command/address, write data and read data bus lines and corresponding to said plurality of memory banks, each of said banks registers having an address register, a write data register, connected to said bank registers, for transferring write data, and a read data register, connected to said bank registers, for transferring read data, each said even numbered memory bank and the respective adjoining odd numbered memory bank are simultaneously accessed by said address register responsive to said two-word command, said even numbered memory bank reads out data at the timing of specific cycles after said access, and said odd numbered memory bank reads out data after a delay of one cycle compared with the reading out of said even numbered memory bank, under the control of said control pipeline register.

Claim 12

A memory access control system as claimed in claim 2, wherein each said even number memory bank comprises address register means and write data register means for providing their contents as inputs to the respective even memory bank, and counter circuit means for holding the contents of said address register means and said writer data register means.

Claim 13

A memory access control system as claimed in claim 2, wherein each said odd number memory bank comprises address register means and write data register for providing their contents as inputs to the respective odd memory bank, and counter circuit means for holding the contents of said address register and said write data register and for delaying write and read timing to the respective odd memory bank by only one cycle.

Claim 14

A memory access control system as claimed in claim 3, wherein each said two-word command comprises a sixteen-byte command constituted by two eight-byte commands.

Claim 15

A memory access control system as claimed in claim 3, further comprising memory control means for controlling said command/address register, said write data register and said read data register in said activating means.

Claim 16

A memory access control system as claimed in claim 1, wherein said write data bus line and read data bus line are used simultaneously for parallel processing of data.

Claim 17

A memory access control system, comprising: first and second memory banks each operating independently of the other; a processing unit issuing a single access request signal including a two-word transfer command and an address; a single data transfer bus connecting said processing unit to first and second memory banks; and transfer activation means for transfer activation, connected between said processing unit and said first and second memory banks, receiving the two word transfer command and the address from the processing unit, and including means for decoding the two-word transfer command and the address, and means for activating said first and second memory banks in response to the two-word transfer command to transfer data of the second memory bank over the single data transfer bus to said processing unit after the data of the first memory bank is transferred over the single data transfer bus, said activating means comprising: detecting means for detecting that a single access request having a first address for one group is a double word access; means for generating a second address for the other group in response to detection of the double word access; and starting means for starting access in dependence on the first address and starting access in dependence on the second address.

Claim 18

A memory access control system, comprising: first and second memory banks each operating independently of the other; a processing unit issuing a single access request signal including a two-word transfer command and an address; a single data transfer bus connecting said processing unit to first and second memory banks; and transfer activation means for transfer activation, connected between said processing unit and said first and second memory banks, receiving the two word transfer command and the address from the processing unit, and including means for decoding the two-word transfer command and the address, and means for activating said first and second memory banks in response to the two-word transfer command to transfer data of the second memory bank over the single data transfer bus to said processing unit after the data of the first memory bank is transferred over the single data transfer bus, said activating means comprising: detecting means for detecting that a single access request having a first address for one group is a double word access; means for generating a second address for the other group in response to detection of the double word access; and starting means for starting access in dependence on the first address and starting access in dependence on the second address.

Claim 19

A system as claimed in claim 13, further comprising delay means, provided in said second memory bank, for delaying transfer of the data of said second memory bank for a predetermined time period in response to activation by said transfer activation means.