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US4866567A
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High frequency integrated circuit channel capacitor
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1989-01-06
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Granted: 1989-09-12
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Expires: 2009-01-06
Abstract
Abstract A high frequency integrated circuit channel capacitor structure comprised of interdigitated field effect transistor gate electrodes and source/drain regions of minimum dimension and respective common connection. The multiplicity of parallel connected capacitive regions between the polysilicon gate electrode and a channel region in the substrate provide precisely controlled capacitors with exceptionally low resistance. Metallization contacts to the gate polysilicon and source/drain regions at each interleaved pattern, together with minimum channel length dimensions, minimizes the capacitive resistance. A CMOS configuration is also feasible.
Inventors
- 👤 Harold S. Crafts
- 👤 Mark Q. Scaggs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:00
CPC Classifications
H; H10; H10D; H10D88/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
85 words
A high frequency integrated circuit channel capacitor, comprising: 1 a first lightly doped semiconductor substrate region of first conductivity type; a multiplicity of electrically common connected field effect first gate electrodes separated by gate dielectric from underlying channel regions defined in the first semiconductor substrate, forming a first electrode of the capacitor; and a multiplicity of commonly connected source/drain diffused regions of second conductivity type in the semiconductor substrate individually located between successive first gate electrode channel regions, forming a second electrode of the capacitor.
Claim 2
Dependent Claim
85 words
A high frequency integrated circuit channel capacitor, comprising: 1 a first lightly doped semiconductor substrate region of first conductivity type; a multiplicity of electrically common connected field effect first gate electrodes separated by gate dielectric from underlying channel regions defined in the first semiconductor substrate, forming a first electrode of the capacitor; and a multiplicity of commonly connected source/drain diffused regions of second conductivity type in the semiconductor substrate individually located between successive first gate electrode channel regions, forming a second electrode of the capacitor.
Claim 3
Dependent Claim
17 words
The apparatus recited in claim 1, wherein the first gate electrodes define thereunder channels of minimum dimension.
Claim 4
Dependent Claim
21 words
The apparatus recited in claim 2, wherein the diffused regions between successive first gate electrode channel regions are of minimum dimension.
Claim 5
Dependent Claim
32 words
The apparatus recited in claim 3, wherein the first gate electrodes are composed of doped polysilicon, are interdigitated in structure, and have channel regions with a width/length ration in excess of 10.
Claim 6
Dependent Claim
95 words
The apparatus recited in claim 1, further including: a second lightly doped semiconductor substrate region of second conductivity type; a multiplicity of commonly connected field effect second gate electrodes separated by gate dielectric from underlying channel regions defined in the second substrate region, forming a further part of the first electrode of the capacitor; and a multiplicity of commonly connected source/drain diffused regions of first conductivity type in the semiconductor substrate of second conductivity type individually located between successive second gate electrode channel regions, forming a further part of the second electrode of the capacitor.
Claim 7
Dependent Claim
17 words
The apparatus recited in claim 5, wherein the second gate electrodes define thereunder channels of minimum dimension.
Claim 8
Dependent Claim
21 words
The apparatus recited in claim 6, wherein the diffused regions between corresponding successive gate electrode channel regions are of minimum dimension.
Claim 9
Dependent Claim
32 words
The apparatus recited in claim 7, wherein the gate electrodes are composed of doped polysilicon, are correspondingly interdigitated in structure, and have channel regions with a width/length ration in excess of 10.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-11 | 1993-03-13 | 1993-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-11 | 1997-03-13 | 1997-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-11 | 2001-03-13 | 2001-09-12 | $7700.00 | Window Closed / Lapsed |