Error control apparatus using restore memory for recovering from parity discordances in transmissions between controller and real-time I/O devices

Claim 1

An input/output device for monitoring transmission of information between a processor of a programmable controller, input circuits connected to sensors and output circuits connected to actuators, said processor comprising a central unit connected to a bus, means for transmitting to said bus first digital words in a parallel transmitting mode, means for generating for each of said first digital words, a first parity signal representative of the parity of this first digital word, means for comparing said first parity signal with a second parity signal transmitted by the device to the central unit, and means for transmitting to the device a control signal only when the first parity signal is concordant with the second parity signal, said input/output device comprising: i-first connection areas connected to the bus so as to receive the first digital words; ii-second connection areas connected to said input circuits so as to receive second digital words proceeding from the sensors; iii-third connection areas connected to said output circuits so as to transmit third digital words to the actuators; iv-first electronic circuits which connect said first connection areas to said second connection areas and which comprise means for deriving from said second digital words, input digital words, and means for transmitting in a parallel transmitting mode these input digital words to said processor through said first connection area and through said bus; v-second electronic circuits connecting said first connection areas to the third connection areas, said second electronic circuit comprising at least a memory register having input terminals connected to the first connection areas so as to receive each of said first digital words, a memory unit, means for storing into the memory unit each digital word present on the input terminals, only upon reception of the said control signal, and output terminals which are connected to means for generating on the third connecting areas a third digital word representative of the first digital word stored in the memory unit, and vi-a parity generator comprising means for calculating a second parity for each of the first digital words applied on the first connection areas, means for generating a second parity signal representative of this second parity, and means for transmitting the second parity signal to the central unit.