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JPS54103643A Expired / Lapsed JP ⏱️ 0.0 years remaining

Process input/output device

Assignee: Toshiba Corp
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Filing: 1978-02-01
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Granted: —
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Expires: 1998-02-01
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Abstract

Abstract PURPOSE: To enhance the reliability of the input/output data as well as to ensure an early detection of the fault for the process input/output device which performs transfer of the process input/output data by providing a parity function to the bus of the process input/output device. CONSTITUTION: In the case of output of the data, the parity bit is applied to the data from parity generator 7, and the data is delivered to bus 4. When output board 2 receives this data, a checking is given by parity checker 8 to deliver the parity error signal. Thus, the data is repealed, and the parity error line of bus 4 is made active. In the case of input, the parity bit is generated at input board 3 and then applied to the data to be delivered to bus 4. Checker 8 of controller 1 checks the data to deliver the parity error signal. The logical sum is secured between the parity error signal and the parity error line. Thus, controller 1 can know that some error takes place to the input/output via the presence of the signal, and then informs the fault to CPU. As a result, the faulty area can be detected through relief of the error. COPYRIGHT: (C)1979,JPO&Japio

Inventors

  • 👤 Yukio Urushibata

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 15:13
CPC Classifications
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