US4507784A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing systems
Assignee: Fujitsu Services Ltd
•
Filing: 1983-05-18
•
Granted: 1985-03-26
•
Expires: 2003-05-18
Abstract
Abstract A data processing system consists of a number of modules such as integrated circuit chips, each of which receives a clock signal. Each module contains a checking circuit producing a failure signal which indicates whether or not the module is operating correctly. The clock signal is used to invert the sense of this failure signal in successive clock periods. Thus, the failure signal normally alternates between two values in successive clock periods, and its phase relative to the clock signal denotes whether or not a failure has been detected. However, if the clock supply to a module fails, or if the checking circuit itself fails, the failure signal from that module no longer alternates, but is frozen at one or other of the two values. This allows failure of the clock supply or of the checking circuit to be detected.
Inventors
- 👤 Brian J. Procter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:20
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
71 words
A data processing system comprising a plurality of modules, each module comprising: (a) means for receiving a clock signal for controlling the timing of the module, (b) checking means for monitoring the operation of the module and producing a failure signal to indicate whether or not the module is operating correctly, and (c) means responsive to the clock signal for inverting the sense of the failure signal in successive clock periods.
Claim 2
Dependent Claim
71 words
A data processing system comprising a plurality of modules, each module comprising: (a) means for receiving a clock signal for controlling the timing of the module, (b) checking means for monitoring the operation of the module and producing a failure signal to indicate whether or not the module is operating correctly, and (c) means responsive to the clock signal for inverting the sense of the failure signal in successive clock periods.
Claim 3
Dependent Claim
59 words
A system according to claim 1 wherein the means for inverting the sense of the failure signal in successive clock periods comprises: (a) means responsive to the clock signal for producing a control signal which alternates between opposite binary values in successive clock periods, and (b) means for applying the control signal to one input of the checking means.
Claim 4
Dependent Claim
15 words
A system according to claim 2 wherein said checking means is a parity checking circuit.
Claim 5
Dependent Claim
15 words
A system according to claim 1 wherein each said module is an integrated circuit chip.
Claim 6
Dependent Claim
40 words
A system according to claim 1 wherein each module includes a plurality of checking means for producing a plurality of individual failure signals, and means for combining the individual failure signals to produce an overall failure signal for the module.
Claim 7
Dependent Claim
26 words
A system according to claim 5 including means responsive to the clock signal for inverting the sense of each individual failure signal in successive clock periods.
Claim 8
Dependent Claim
65 words
A system according to claim 6 wherein the means for combining the individual failure signals comprises a first gate for sensing when all the failure signals are at one binary level, a second gate for sensing when all the failure signals are at the opposite binary level, and a data selector for selecting the outputs of the first and second gates during alternate clock periods.
Claim 9
Dependent Claim
24 words
A system according to claim 1 further comprising means for combining the failure signals from the modules to produce an overall system failure signal.
Claim 10
Dependent Claim
67 words
A system according to claim 8 wherein the means for combining the failure signals from the modules comprises a first gate for sensing when all the failure signals are at one binary level, a second gate for sensing when all the failure signals are at the opposite binary level, and a data selector for selecting the outputs of the first and second gates during alternate clock periods.
Claim 11
Dependent Claim
63 words
A system according to claim 1 wherein each module comprises: (a) a plurality of internal registers, (b) means operative in response to a mode control signal to link all the registers together to form a shift register with a serial data output, and (c) a data selector, for selecting either the failure signal or the serial data output for output from the module.
Claim 12
Dependent Claim
64 words
A data processing module, comprising (a) means for receiving a clock signal for controlling the timing of the module, (b) checking means for monitoring the operation of the module and producing a failure signal to indicate whether or not the module is operating correctly, and (c) means responsive to the clock signal for inverting the sense of the failure signal in successive clock periods.
Claim 13
Dependent Claim
64 words
A data processing module, comprising (a) means for receiving a clock signal for controlling the timing of the module, (b) checking means for monitoring the operation of the module and producing a failure signal to indicate whether or not the module is operating correctly, and (c) means responsive to the clock signal for inverting the sense of the failure signal in successive clock periods.
Claim 14
Dependent Claim
110 words
A data processing module comprising: (a) means for receiving a clock signal for controlling the timing of the module, (b) means responsive to the clock signal for producing an output signal which alternates between two values during successive clock periods in a predetermined phase relationship with the clock signal and which, upon failure of the clock supply to the module, becomes static at one of said values, and (c) checking means for monitoring the operation of the module and operative, upon detection of a failure within the module, to invert the sense of said output signal, thereby shifting the phase relationship of the output signal relative to the clock signal.
Claim 15
Dependent Claim
110 words
A data processing module comprising: (a) means for receiving a clock signal for controlling the timing of the module, (b) means responsive to the clock signal for producing an output signal which alternates between two values during successive clock periods in a predetermined phase relationship with the clock signal and which, upon failure of the clock supply to the module, becomes static at one of said values, and (c) checking means for monitoring the operation of the module and operative, upon detection of a failure within the module, to invert the sense of said output signal, thereby shifting the phase relationship of the output signal relative to the clock signal.
References Cited (Backward Citations)
US4081662A
Cited
US4122441A
Cited
US4144448A
Cited
US4328583A
Cited
US4342112A
Cited
US4392226A
Cited
US4468768A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-03-25 | 1988-09-24 | 1989-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-03-25 | 1992-09-24 | 1993-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-03-25 | 1996-09-24 | 1997-03-26 | $7700.00 | Window Closed / Lapsed |