Viad chip capacitor and method for making same

Claim 1

A two pole viad chip capacitor that is activatable from either of its sides, comprising: (a) a plurality of ceramic layers in a stack, each and every layer having only two vias, a first via in a first region of each layer and a second via in a second region of each layer; (b) a first conductor in each of the first vias; (c) a second conductor in each of the second vias; (d) a stack of first capacitor plates, the first plates being on first alternate ceramic layers, each first plate being in electrical contact with a first conductor; and (e) a stack of second capacitor plates, the second plates being on second alternate ceramic layers that are interdigitated with the first alternate ceramic layers, each second plate being in electrical contact with a second conductor.

Claim 4

A method of making a two pole viad chip capacitor that is activatable from either of its sides, comprising: (a) punching each and every one of a plurality of ceramic layers to form only two vias, a first via being formed in a first region of each layer and a second via being formed in a second region of each layer; (b) filling the first vias with first conductive material to form a first conductor in each of them; (c) filling the second vias with second conductive material to form a second conductor in each of them; (d) forming a first capacitor plate on each of selected first ceramic layers in electrical contact with a first conductor; (e) forming a second capacitor plate on each of other selected second layers in electrical contact with a second conductor; and (f) stacking the selected ceramic layers so that the first capacitor plates alternate with the second capacitor plates and so that the conductors in the first vias make electrical contact among themselves and so that the conductors in the second vias make electrical contact among themselves.

Claim 5

A method of making a two pole viad chip capacitor that is activatable from either of its sides, comprising: (a) punching each and every one of a plurality of ceramic layers to form only two vias, a first via being formed in a first region of each layer and a second via being formed in a second region of each layer; (b) filling the first vias with first conductive material to form a first conductor in each of them; (c) filling the second vias with second conductive material to form a second conductor in each of them; (d) forming a first capacitor plate on each of selected first ceramic layers in electrical contact with a first conductor; (e) forming a second capacitor plate on each of other selected second layers in electrical contact with a second conductor; and (f) stacking the selected ceramic layers so that the first capacitor plates alternate with the second capacitor plates and so that the conductors in the first vias make electrical contact among themselves and so that the conductors in the second vias make electrical contact among themselves.

Claim 7

A method of making a viad chip capacitor, comprising the steps of: (a) sending ceramic material through a screening mask that has via blocks in it and onto a substrate in order to form a wet ceramic layer having vias in it; (b) drying the ceramic layer to form a viad ceramic layer; (c) filling the vias of the layer with conductive material to form conductors; and (d) forming a capacitor plate on the ceramic layer and in electrical contact with a conductor in the layer.

Claim 8

A method of making a viad chip capacitor, comprising the steps of: (a) sending ceramic material through a screening mask that has via blocks in it and onto a substrate in order to form a wet ceramic layer having vias in it; (b) drying the ceramic layer to form a viad ceramic layer; (c) filling the vias of the layer with conductive material to form conductors; and (d) forming a capacitor plate on the ceramic layer and in electrical contact with a conductor in the layer.

Claim 9

A method of making a viad chip capacitor, comprising the steps of: (a) sending ceramic material through a screening mask that has via blocks in it and onto a substrate in order to form a wet first ceramic layer having first vias in it; (b) drying the first ceramic layer to form a first viad ceramic layer; (c) filling the first vias of the first ceramic layer with conductive material in order to form first and second conductors in the first vias; (d) forming a capacitor plate on the first ceramic layer and in electrical contact with the first conductor in the first layer; (e) sending ceramic material through the screening mask and onto the first ceramic layer in order to form a wet second ceramic layer having second vias in it, the second vias being in alignment with the first vias; (f) drying the second ceramic layer to form a sandwich of ceramic layers; (g) filling the second vias of the second ceramic layer with conductive material in order to form first and second conductors in the second vias; and (h) forming a capacitor plate on the second ceramic layer and in electrical contact with the second conductor in the second layer.

Claim 10

A method of making a viad chip capacitor, comprising the steps of: (a) sending ceramic material through a screening mask that has via blocks in it and onto a substrate in order to form a wet first ceramic layer having first vias in it; (b) drying the first ceramic layer to form a first viad ceramic layer; (c) filling the first vias of the first ceramic layer with conductive material in order to form first and second conductors in the first vias; (d) forming a capacitor plate on the first ceramic layer and in electrical contact with the first conductor in the first layer; (e) sending ceramic material through the screening mask and onto the first ceramic layer in order to form a wet second ceramic layer having second vias in it, the second vias being in alignment with the first vias; (f) drying the second ceramic layer to form a sandwich of ceramic layers; (g) filling the second vias of the second ceramic layer with conductive material in order to form first and second conductors in the second vias; and (h) forming a capacitor plate on the second ceramic layer and in electrical contact with the second conductor in the second layer.