Decoupling capacitor for pin grid array package

Claim 2

A decoupling capacitor for use with a pin grid array package, the pin grid array package having an array of pins extending from one side thereof and surrounding a central pin free area of predetermined size, at least some of the pins surrounding the central pin free area being first and second voltage level pins, the capacitor including: at least one multilayer capacitor chip having interleaved layers of conductive material and dielectric material with alternating layers of conductive material being electrically connected and defining first and second groups of conductive layers, each of said first and second groups having at least one exposed conductive layer defining a first exposed conductive layer and a second exposed conductive layer; a first conductor in electrical contact with said first exposed conductive layer and defining a first voltage level conductor; a second conductor in electrical contact with said second exposed conductive layer and defining a second voltage level conductor; a plurality of first leads in a predetermined configuration in electrical contact with said first conductor and extending outwardly therefrom; a plurality of second leads in a predetermined configuration in electrical contact with said second conductor and extending outwardly therefrom; the configurations of said first and second leads corresponding to configurations of first and second voltage levels of pins of the pin grid array package; an insulating material surrounding said dielectric body and conductors, said first and second leads extending through said insulating material; and said at least one multilayer capacitor chip, first conductor, second conductor and insulating material defining an insulated assembly, the size of said insulated assembly being less than the size of the central pin free area.

Claim 3

The capacitor of claim 1 wherein: said insulated assembly is substantially rectangular.

Claim 4

The capacitor of claim 2 wherein: said insulated assembly is substantially square.

Claim 5

The capacitor of claim 1 wherein: said leads extend outwardly and downwardly perpendicular to said conductors.

Claim 6

The capacitor of claim 1 wherein: each of said leads comprises a tab having an opening therethrough for receiving one of said pins from said pin grid array package.

Claim 7

The capacitor of claim 1 including: stand off means provided on said insulated assembly.

Claim 8

The capacitor of claim 1 wherein: said dielectric body, first conductor, second conductor, first leads, second leads and insulating material have a size which is less than the size of the central pin free area.

Claim 9

The capacitor of claim 1 wherein: said first exposed conductive layers and said second exposed conductive layers are substantially parallel to each other and to said first and second conductors.

Claim 10

The capacitor of claim 8 wherein: said dielectric layers of said multilayer capacitor chip include a pair of opposed end surfaces and top and bottom surfaces; a plurality of parallel conductive layers interleaved within said dielectric material, said interleaved parallel conductive layers being parallel to said first and second exposed conductive layers; said conductive layers being alternately spaced from one or the other of said opposed end surfaces of said dielectric layers; a pair of opposed vias through said dielectric material respectively electrically interconnecting said alternating layers of said first group of conductive layers and said alternating layers of said second group of conductive layers.

Claim 11

The capacitor of claim 9 including: an electroless plating layer over at least a portion of said top and bottom surface of said dielectric material and in said vias.

Claim 12

The capacitor of claim 8 wherein: said dielectric layers of said multilayer capacitor chip include a pair of opposed end surfaces and top and bottom surfaces; a plurality of parallel conductive layers interleaved within said dielectric material with said first exposed conductive layer on said top surface of said ceramic material and said second exposed conductive layer on said bottom surface of said dielectric material; a first conductive end termination on one of said opposed end surfaces of said dielectric material and a second conductive end termination on the other of said opposed end surfaces of said dielectric material; alternating layers of said interleaved conductive layers terminating at said first and second conductive end terminations with said top and bottom conductive surfaces being connected and substantially transverse to respective first and second conductive end terminations whereby a gap is defined between each of said end terminations and one of said first or second conductive layers.

Claim 13

The capacitor of claim 11 including: an electrically insulative cap being provided over each of said first and second conductive end terminations wherein said conductive end terminations are encapsulated and wherein electrical bridging between said top and bottom conductive surface and said first and second conductive end termination is precluded by said insulative caps.

Claim 14

The capacitor of claim 12 wherein: said insulative cap is comprised of a material selected from the group comprising glass and epoxy.

Claim 15

The capacitor of claim 11 wherein: said multilayer capacitor chip has diagonally opposed corners in said gap; and wherein a portion of said diagonal corners is removed.

Claim 16

The capacitor of claim 11 wherein: said interleaved layers of dielectric material have a predetermined thickness; and wherein said layers of dielectric material adjacent said top and bottom surfaces have a larger thickness relative to the other layers of dielectric material.

Claim 17

The capacitor of claim 1 including: an electrically insulative spacing layer, said spacing layer having at least one opening therethrough for receiving said at least one multilayer capacitor chip, said spacing layer being sandwiched between said first and second conductors with said opening communicating between said first and second conductors.

Claim 18

The capacitor of claim 1 including: holes disposed through said first and second conductors, said holes communicating with said first and second exposed conductive layers.

Claim 19

The capacitor of claim 17 including: electrically conductive material in said holes thereby electrically connecting said first and second conductors with respective of said first and second exposed conductive layers.

Claim 20

The capacitor of claim 1 including: a plurality of multilayer capacitor chips sandwiched between said first and second conductors.

Claim 21

The capacitor of claim 1 wherein: said dielectric material is a ceramic material.

Claim 22

An electronic subassembly comprising: a pin grid array package, said pin grid array package having an array of pins extending from one side thereof and surrounding a central pin free area of predetermined size, at least some of the pins surrounding the central pin free area being first and second voltage level pins; a circuit board, said circuit board having first spaced holes receiving said pin grid array package pins; and decoupling capaciator means, said decoupling capacitor means being aligned with said central pin free area of said pin grid array package and electrically communicating with said circuit board, said capacitor means comprising: at least one multilayer capacitor chip having interleaved layers of conductive material and dielectric material with alternating layers of conductive material being electrically connected and defining first and second groups of conductive layers, each of said first and second groups having at least one exposed conductive layer defining a first exposed conductive layer and a second exposed conductive layer; a first conductor in electrical contact with said first exposed conductive layer and defining a first voltage level conductor; a second conductor in electrical contact with said second exposed conductive layer and defining a second voltage level conductor; a plurality of first leads in a predetermined configuration in electrical contact with said first conductor and extending outwardly therefrom; a plurality of second leads in a predetermined configuration in electrical contact with said second conductor and extending outwardly therefrom; the configurations of said first and second leads corresponding to configurations of first and second voltage levels of pins of said pin grid array package; an insulating material surrounding said dielectric body and conductors, said first and second leads extending through said insulating material; and said at least one multilayer capacitor chip, first conductor, second conductor and insulating material defining an insulated assembly, the size of said insulated assembly being less than the size of the central pin free area.

Claim 23

An electronic subassembly comprising: a pin grid array package, said pin grid array package having an array of pins extending from one side thereof and surrounding a central pin free area of predetermined size, at least some of the pins surrounding the central pin free area being first and second voltage level pins; a circuit board, said circuit board having first spaced holes receiving said pin grid array package pins; and decoupling capaciator means, said decoupling capacitor means being aligned with said central pin free area of said pin grid array package and electrically communicating with said circuit board, said capacitor means comprising: at least one multilayer capacitor chip having interleaved layers of conductive material and dielectric material with alternating layers of conductive material being electrically connected and defining first and second groups of conductive layers, each of said first and second groups having at least one exposed conductive layer defining a first exposed conductive layer and a second exposed conductive layer; a first conductor in electrical contact with said first exposed conductive layer and defining a first voltage level conductor; a second conductor in electrical contact with said second exposed conductive layer and defining a second voltage level conductor; a plurality of first leads in a predetermined configuration in electrical contact with said first conductor and extending outwardly therefrom; a plurality of second leads in a predetermined configuration in electrical contact with said second conductor and extending outwardly therefrom; the configurations of said first and second leads corresponding to configurations of first and second voltage levels of pins of said pin grid array package; an insulating material surrounding said dielectric body and conductors, said first and second leads extending through said insulating material; and said at least one multilayer capacitor chip, first conductor, second conductor and insulating material defining an insulated assembly, the size of said insulated assembly being less than the size of the central pin free area.

Claim 24

The subassembly of claim 21 wherein: said decoupling capacitor means is interposed between said central pin free area of said pin grid array package and said circuit board.

Claim 25

The subassembly of claim 21 wherein: said insulated assembly is substantially rectangular.

Claim 26

The subassembly of claim 23 wherein: said insulated assembly is substantially square.

Claim 27

The subassembly of claim 21 wherein: said leads extend outwardly and downwardly perpendicular to said conductors.

Claim 28

The subassembly of claim 21 wherein: each of said leads comprises a tab having an opening therethrough for receiving one of said pins from said pin grid array package.

Claim 29

The subassembly of claim 21 including: stand off means provided on said insulated assembly.

Claim 30

The subassembly of claim 27 wherein: said standoff means defines a space between said decoupling capacitor and said circuit board.

Claim 31

The subassembly of claim 21 including: second spaced holes in said circuit board for receiving said first and second voltage level leads of said decoupling capacitor.

Claim 32

The subassmebly of claim 29 wherein: said dielectric body, first conductor, second conductor, first leads, second leads and insulating material have a size which is less than the size of the central pin free area.

Claim 33

The subassembly of claim 21 wherein: said dielectric body, first conductor, second conductor, first leads, second leads and insulating material have a size which is less than the size of the central pin free area.

Claim 34

The subassembly of claim 21 wherein: said first and second voltage level leads of said decoupling capacitor are received in the same holes as the corresponding first and second volatage level pins of said pin grid array package.

Claim 35

The subassembly of claim 21 wherein: said first exposed conductive layers and said second exposed conductive layers are substantially parallel to each other and to said first and second conductors.

Claim 36

The subassembly of claim 33 wherein: said dielectric layers of said multilayer capacitor chip include a pair of opposed end surfaces and top and bottom surfaces; a plurality of parallel conductive layers interleaved within said dielectric material, said interleaved parallel conductive layers being parallel to said first and second exposed conductive layers; said conductive layers being alternately spaced from one or the other of said opposed end surfaces of said dielectric layers; a pair of opposed vias through said dielectric material respectively electrically interconnecting said alternating layers of said first group of conductive layers and said alternating layers of said second group of conductive layers.

Claim 37

The subassembly of claim 34 including: an electroless plating layer over at least a portion of said top and bottom surface of said dielectric material and in said vias.

Claim 38

The subassembly of claim 33 wherein: said dielectric layers of said multilayer capacitor chip include a pair of opposed end surfaces and top and bottom surfaces; a plurality of parallel conductive layers interleaved within said dielectric material with said first exposed conductive layer on said top surface of said ceramic material and said second exposed conductive layer on said bottom surface of said dielectric material; a first conductive end termination on one of said opposed end surfaces of said dielectric material and a second conductive end termination on the other of said opposed end surfaces of said dielectric material; alternating layers of said interleaved conductive layers terminating at said first and second conductive end terminations with said top and bottom conductive surfaces being connected and substantially transverse to respective first and second conductive end terminations whereby a gap is defined between each of said end terminations and one of said first or second conductive layers.

Claim 39

The subassembly of claim 36 including: an electrically insulative cap being provided over each of said first and second conductive end terminations wherein said conductive end terminations are encapsulated and wherein electrical bridging between said top and bottom conductive surface and said first and second conductive end termination is precluded by said insulative caps.

Claim 40

The subassembly of claim 37 wherein: said insulative cap is comprised of a material selected from the group comprising glass and epoxy.

Claim 41

The subassembly of claim 36 herein: said multilayer capacitor chip has diagonally opposed corners in said gap; and wherein a portion of said diagonal corners is removed.

Claim 42

The subassembly of claim 36 wherein: said interleaved layers of dielectric material have a predetermined thickness; and wherein said layers of dielectric material adjacent said top and bottom surfaces have a larger thickness relative to the other layers of dielectric material.

Claim 43

The subassembly of claim 21 including: an electrically insulative spacing layer, said spacing layer having at least one opening therethrough for receiving said at least one multilayer capacitor chip, said spacing layer being sandwiched between said first and second conductors with said opening communicating between said first and second conductors.

Claim 44

The subassembly of claim 21 including: holes disposed through said first and second conductors, said holes communicating with said first and second exposed conductive layers.

Claim 45

The subassembly of claim 42 including: electrically conductive material in said holes thereby electrically connecting said first and second conductors with respective of said first and second exposed conductive layers.

Claim 46

The subassembly of claim 21 including: a plurality of multilayer capacitor chips sandwiched between said first and second conductors.

Claim 47

The subassembly of claim 21 wherein: said dielectric material is a ceramic material.