Patent US4864382A successfully refreshed from Google Patents.
US4864382A
Expired / Lapsed
US
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Semiconductor device
Assignee: Hitachi Ltd
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Filing: 1988-01-25
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Granted: 1989-09-05
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Expires: 2008-01-25
Abstract
Abstract A MOS memory is formed in a semiconductor bulk, whereas a barrier semiconductor layer is disposed at the boundary between a MOS memory portion and the semiconductor bulk in order to reduce the effect of undesirable carriers excited by α-particles. The barrier semiconductor layer is designed to permit operation of the memory at low temperature while reducing the incidence of soft errors due to α-particles.
Inventors
- 👤 Masaaki Aoki
- 👤 Kazuo Yano
- 👤 Toshiaki Masuhara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 11:58
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/387; H10B; H10B12/00; H10B12/30; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D62/80; H10D62/83; H10D62/834; Y; Y10; Y10S; Y10S257/00; Y10S257/919
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
132 words
A semiconductor device comprising: (1) a first semiconductor layer containing a first conductivity type which is formed in a semiconductor substrate; (2) a charge accumulation portion disposed in said first semiconductor layer to accumulate information charge of a memory cell; and (3) a barrier semiconductor layer formed in said first semiconductor layer under said charge accumulation portion, wherein said barrier semiconductor layer is defined by a semiconductor layer of the first conductivity type which is partially compensated by an impurity of a second conductivity type which is opposite to said first conductivity type, wherein said first semiconductor layer of said first conductivity type is formed in said semiconductor substrate of said second conductivity type, and wherein said carrier semiconductor layer has a contact with said semiconductor substrate within said first semiconductor layer.
Claim 2
Dependent Claim
132 words
A semiconductor device comprising: (1) a first semiconductor layer containing a first conductivity type which is formed in a semiconductor substrate; (2) a charge accumulation portion disposed in said first semiconductor layer to accumulate information charge of a memory cell; and (3) a barrier semiconductor layer formed in said first semiconductor layer under said charge accumulation portion, wherein said barrier semiconductor layer is defined by a semiconductor layer of the first conductivity type which is partially compensated by an impurity of a second conductivity type which is opposite to said first conductivity type, wherein said first semiconductor layer of said first conductivity type is formed in said semiconductor substrate of said second conductivity type, and wherein said carrier semiconductor layer has a contact with said semiconductor substrate within said first semiconductor layer.
Claim 3
Dependent Claim
77 words
A semiconductor device according to claim 1, wherein an impurity concentration of said first conductivity type is larger than that of said second conductivity type in said semiconductor layer of said first conductivity type of said barrier semiconductor layer, impurities of said first and second conductivity types cancelling each other but said semiconductor layer of said first conductivity type of said barrier semiconductor layer having an electrical characteristic corresponding to said first conductivity type after such cancellation.
Claim 4
Dependent Claim
20 words
A semiconductor device according to claim 2, wherein the operating temperature of said semiconductor device is 100° K. or less.
Claim 5
Dependent Claim
48 words
A semiconductor device according to claim 2, wherein the first semiconductor layer of said first conductivity type is a p-type well region which is formed in said semiconductor substrate of n-type, said barrier semiconductor layer being a p-type semiconductor layer which is partially compensated by an n-type impurity.
Claim 6
Dependent Claim
17 words
A semiconductor device according to claim 4, wherein said charge accumulation portion is an n-type semiconductor layer.
Claim 7
Dependent Claim
20 words
A semiconductor device according to claim 1, wherein the operating temperature of said semiconductor device is 100° K. or less.
Claim 8
Dependent Claim
95 words
A semiconductor device comprising: (1) a first semiconductor layer containing a first impurity of a first conductivity type which is formed in a semiconductor substrate; (2) a charge accumulation portion disposed in said first semiconductor layer to accumulate information charge of a memory cell; and (3) a barrier semiconductor layer formed in the first semiconductor layer under said charge accumulation portion, wherein said barrier semiconductor layer contains a second impurity of the same conductivity type as that of said first impurity which has a deep impurity level, said second impurity having a shallow impurity level.
Claim 9
Dependent Claim
95 words
A semiconductor device comprising: (1) a first semiconductor layer containing a first impurity of a first conductivity type which is formed in a semiconductor substrate; (2) a charge accumulation portion disposed in said first semiconductor layer to accumulate information charge of a memory cell; and (3) a barrier semiconductor layer formed in the first semiconductor layer under said charge accumulation portion, wherein said barrier semiconductor layer contains a second impurity of the same conductivity type as that of said first impurity which has a deep impurity level, said second impurity having a shallow impurity level.
Claim 10
Dependent Claim
16 words
A semiconductor device according to claim 5, wherein said first and second impurities are of p-type.
Claim 11
Dependent Claim
23 words
A semiconductor device according to claim 6, wherein the impurity concentration of said second impurity is higher than that of said first impurity.
Claim 12
Dependent Claim
20 words
A semiconductor device according to claim 7 wherein the operating temperature of said semiconductor device is 100° K. or less.
Claim 13
Dependent Claim
134 words
A semiconductor device comprising: (1) a first semiconductor layer containing a first impurity of a first conductivity type which is formed in a semiconductor substrate; (2) a charge accumulation portion disposed in said first semiconductor layer to accumulate information charge of a memory cell; and (3) a barrier semiconductor layer formed in said first semiconductor layer under said charge accumulation portion, wherein said barrier semiconductor layer contains a second impurity of the same conductivity type as that of said first impurity which has a shallow impurity level, said second impurity having a deep impurity level, wherein said first semiconductor layer of said first conductivity type is formed in said semiconductor substrate of said second conductivity type, and wherein said barrier semiconductor layer has a contact with said semiconductor substrate within said first semiconductor layer.
Claim 14
Dependent Claim
134 words
A semiconductor device comprising: (1) a first semiconductor layer containing a first impurity of a first conductivity type which is formed in a semiconductor substrate; (2) a charge accumulation portion disposed in said first semiconductor layer to accumulate information charge of a memory cell; and (3) a barrier semiconductor layer formed in said first semiconductor layer under said charge accumulation portion, wherein said barrier semiconductor layer contains a second impurity of the same conductivity type as that of said first impurity which has a shallow impurity level, said second impurity having a deep impurity level, wherein said first semiconductor layer of said first conductivity type is formed in said semiconductor substrate of said second conductivity type, and wherein said barrier semiconductor layer has a contact with said semiconductor substrate within said first semiconductor layer.
Claim 15
Dependent Claim
16 words
A semiconductor device according to claim 11, wherein said first and second impurities are of p-type.
Claim 16
Dependent Claim
20 words
A semiconductor device according to claim 11, wherein the operating temperature of said semiconductor device is 100° K. or less.
Claim 17
Dependent Claim
20 words
A semiconductor device according to claim 4, wherein the operating temperature of said semiconductor device is 100° K. or less.
Claim 18
Dependent Claim
20 words
A semiconductor device according to claim 5, wherein the operating temperature of said semiconductor device is 100° K. or less.
Claim 19
Dependent Claim
20 words
A semiconductor device according to claim 8, wherein the operating temperatures of said semiconductor device is 100° K. or less.
Claim 20
Dependent Claim
20 words
A semiconductor device according to claim 9, wherein the operating temperature of said semiconductor device is 100° K. or less.
Claim 21
Dependent Claim
20 words
A semiconductor device according to claim 12, wherein the operating temperature of said semiconductor device is 100° K. or less.
References Cited (Backward Citations)
US4649408A
Cited
US4424526A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1992-09-04 | 1993-03-06 | 1993-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-04 | 1997-03-06 | 1997-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-04 | 2001-03-06 | 2001-09-05 | $7700.00 | Window Closed / Lapsed |