US4862485A
Expired / Lapsed
US
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Quotient phase-shift processor for digital phase-locked-loops
Assignee: National Semiconductor Corp
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Filing: 1987-10-14
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Granted: 1989-08-29
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Expires: 2007-10-14
Abstract
Abstract A quotient phase-shift processor is provided which includes novel techniques for realizing phase corrections of a digital phase-locked-loop. A binary phase-detector of the "early-late" type is combined with range-phase-detector circuitry to generate a variable lock acquisition speed. Phase measure and speed control are performed by incremental manipulation which feeds a novel "quotient" processor. The quotient processor integrates the incremental phase errors and performs phase corrections in a nonperiodic fashion, resulting in lower effective proportional loop gain than that provided in standard phase-locked-loops. Wide capture-range and low jitter are obtained by dynamically varying a loop time constant. Pattern dependent noise is reduced by a novel gating technique. High crystal-frequency requirements are reduced, extending the spectral application of digital phase-locked-loops.
Inventors
- 👤 Jesus Guinea
- 👤 Hee Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:50
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0991; H03L7/085; H03L7/093
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
76 words
A quotient digital phase locked loop, comprising: (a) binary phase detector means which compares an incoming signal to an internally-generated baud clock signal to provide a phase error bit sequence which indicates whether the phase of the incoming signal is early or late with respect to the phase of the baud clock signal; and (b) a digital controlled clock which integrates the phase error bit sequence to effect nonperiodic phase manipulation of the baud clock signal.
Claim 2
Dependent Claim
76 words
A quotient digital phase locked loop, comprising: (a) binary phase detector means which compares an incoming signal to an internally-generated baud clock signal to provide a phase error bit sequence which indicates whether the phase of the incoming signal is early or late with respect to the phase of the baud clock signal; and (b) a digital controlled clock which integrates the phase error bit sequence to effect nonperiodic phase manipulation of the baud clock signal.
Claim 3
Dependent Claim
131 words
A quotient digital phase locked loop as in claim 1 wherein the digital controlled clock includes quotient processor means which divides a sequential accumulator value by a divisor constant each period defined by a crystal clock input to the digital controlled clock, the division resulting in a quotient value and a remainder value, the quotient value being only 0 or 1, the remainder value for successive divisions being added until the sum of the remainder values equals or exceeds a predetermined value, the quotient value equalling 0 only when the remainder value sum equals or exceeds the predetermined value, resulting in a quotient value bit stream comprising a sequence of 1s and nonperiodic 0s, the quotient value bit stream being utilized to effect nonperiodic phase manipulation of the baud clock signal.
Claim 4
Dependent Claim
39 words
A quotient digital phase locked loop as in claim 1 and further including a range-phase detector which generates an output indicative of whether the phase of the output of the digital controlled clock is within a predetermined phase range.
Claim 5
Dependent Claim
29 words
A quotient digital phase locked loop as in claim 3 wherein the range-phase-detector output is utilized to dynamically change the frequency of phase manipulation of the baud clock signal.
Claim 6
Dependent Claim
22 words
A quotient digital phase locked loop as in claim 1 and further including means for avoiding phase manipulation during a predefined condition.
Claim 7
Dependent Claim
22 words
A quotient digital phase locked loop as in claim 1 and further including means for disabling phase manipulation during a predetermined period.
Claim 8
Dependent Claim
29 words
A quotient digital phase locked loop as in claim 1 and further including means for dynamically varying the loop time constant to obtain wide capture range and low jitter.
Claim 9
Dependent Claim
18 words
A quotient digital phase locked loop as in claim 5 wherein the predefined condition is a lack-of-strobe condition.
Claim 10
Dependent Claim
23 words
A quotient digital phase locked loop as in claim 6 wherein the predetermined period is a period when no timing information is available.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-28 | 1993-02-27 | 1993-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-28 | 1997-02-27 | 1997-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-28 | 2001-02-27 | 2001-08-29 | $7700.00 | Window Closed / Lapsed |