Patent US4860262A successfully refreshed from Google Patents.
US4860262A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cache memory reset responsive to change in main memory
Assignee: Texas Instruments Inc
•
Filing: 1987-08-05
•
Granted: 1989-08-22
•
Expires: 2007-08-05
Abstract
Abstract A circuit for resetting a multi-bit word in a digital memory at a selected address receives a word reset signal to cause entry into the selected address of a multi-bit word wherein all the bits are set to the same level and a parity bit is set to a value corresponding to parity in the multi-bit word. The circuit includes a parity generator which receives a multi-bit input data word and generates at least one parity bit therefrom. During a normal write operation, the multi-bit input data word and the parity bit are written into the digital memory at the selected address. During a word reset signal, output from the parity generator and the multi-bit input data word are blocked from entry into the memory.
Inventors
- 👤 Edison H. Chiu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:38
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1064; G11; G11C; G11C7/00; G11C7/20
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
177 words
A circuit for writing a multi-bit word into a digital memory at a selected address upon receipt of a write command and responsive to a word reset signal for resetting a multi-bit word that includes at least one parity bit in the digital memory at a selected address, comprising: (a) internal data memory circuit means for receiving a multi-bit word and responsive to reception of said write command to write the multi-bit word into the digital memory at a selected address; (b) parity generator means connected to receive a multi-bit input data word and to generate at least one parity bit therefrom; and (c) resetting means responsive to receipt of said multi-bit word, said parity bit, and said word reset signal to write a reset multi-bit word to the internal data memory circuit means, all the bits of said word being set to a predetermined level and the parity bit being set to said predetermined level corresponding to parity for the reset multi-bit word for writing into the digital memory in the presence of the write command.
Claim 2
Dependent Claim
177 words
A circuit for writing a multi-bit word into a digital memory at a selected address upon receipt of a write command and responsive to a word reset signal for resetting a multi-bit word that includes at least one parity bit in the digital memory at a selected address, comprising: (a) internal data memory circuit means for receiving a multi-bit word and responsive to reception of said write command to write the multi-bit word into the digital memory at a selected address; (b) parity generator means connected to receive a multi-bit input data word and to generate at least one parity bit therefrom; and (c) resetting means responsive to receipt of said multi-bit word, said parity bit, and said word reset signal to write a reset multi-bit word to the internal data memory circuit means, all the bits of said word being set to a predetermined level and the parity bit being set to said predetermined level corresponding to parity for the reset multi-bit word for writing into the digital memory in the presence of the write command.
Claim 3
Dependent Claim
18 words
The circuit of claim 1 wherein the internal data memory circuit means comprises a plurality of bus gates.
Claim 4
Dependent Claim
40 words
The circuit of claim 2 wherein the plurality of bus gates further comprises a NAND gate for each position of the multi-bit word, including the parity bit, for generating each bit of the reset multi-bit word and the parity bit.
Claim 5
Dependent Claim
31 words
The circuit of claim 3 wherein the plurality of bus gates further comprise a second NAND gate for each position for generating the inverse of each bit and the party bit.
Claim 6
Dependent Claim
41 words
The circuit of claim 1 wherein the parity generator means comprises exclusive OR gate means for receiving the multi-bit data word, and exclusive NOR gate means for receiving the output of the exclusive OR gate means to provide a parity bit.
Claim 7
Dependent Claim
46 words
The circuit of claim 1 wherein the resetting means comprises a NOR gate for each position of the input multi-bit data word and a NAND gate for the parity bit, each of the NOR gates and the NAND gate connected to receive the word reset signal.
Claim 8
Dependent Claim
26 words
The circuit of claim 6 further comprising an inverter for inverting the word reset signal to provide an inverted word reset signal to the NAND gate.
Claim 9
Dependent Claim
40 words
The circuit of claim 1 wherein the resetting means comprises delay means for receiving and delaying the write signal until the reset multi-bit word and the corresponding parity bit have had time to enter the internal data memory circuit means.
Claim 10
Dependent Claim
17 words
The circuit of claim 8 wherein the delay means comprises a pair of inverters connected in series.
Claim 11
Dependent Claim
21 words
The circuit of claim 1 wherein each bit of the reset multi-bit word and the parity bit is set to zero.
References Cited (Backward Citations)
US4099069A
Cited
US4155070A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-21 | 1993-02-20 | 1993-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-21 | 1997-02-20 | 1997-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-21 | 2001-02-20 | 2001-08-22 | $7700.00 | Window Closed / Lapsed |