US4860227A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for measuring characteristics of a device under test
Assignee: Verigy Singapore Pte Ltd
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Filing: 1986-01-30
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Granted: 1989-08-22
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Expires: 2006-01-30
Abstract
Abstract A measurement circuit includes two signal sources, one for generating a test input signal to a DUT and the other for generating a sampling signal. Both sources are coupled to one crystal oscillator and one or both sources may be fractional N oscillators. A phase locked loop stabilizes the sampling signal generated by the fractional N oscillator. The test input signal and the output signal from the DUT are separately mixed with the sampling signal and the resulting sampled signal are converted to digital values by A/D converters and stored in a microprocessor. The stored values can later be compared and analyzed by the microprocessor to determine the characteristics of the DUT.
Inventors
- 👤 Toshio Tamamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 23:34
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2832; G01R31/2834
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
210 words
Apparatus for measuring the characteristics of a device under test, comprising: first generating means for generating a periodic test signal with a period of T, based on a crystal oscillator reference signal, applied to the device under test; second generating means coupled to the reference signal of the first generating means, and comprising a fractional N oscillator, for generating a periodic sampling signal with a period of t=nY+T/m, where n and m are integers, and m is the number of sampling intervals into which the test signal period is divided; first sampling means for receiving the output signal of the device under test and the sampling signal to produce a first signal representing the momentary amplitude values of the output signal; second sampling means for receiving the input signal to the device under test and the sampling signal to produce a second signal representing the momentary amplitude values of the input signal; first converting means for converting the first signal to first digital values; second converting means for converting the second signal to second digital values; processing means coupled to the first and second converting means for receiving the first and second digital values, and for calculating characteristics of the device under test from the first and second digital values.
Claim 2
Dependent Claim
210 words
Apparatus for measuring the characteristics of a device under test, comprising: first generating means for generating a periodic test signal with a period of T, based on a crystal oscillator reference signal, applied to the device under test; second generating means coupled to the reference signal of the first generating means, and comprising a fractional N oscillator, for generating a periodic sampling signal with a period of t=nY+T/m, where n and m are integers, and m is the number of sampling intervals into which the test signal period is divided; first sampling means for receiving the output signal of the device under test and the sampling signal to produce a first signal representing the momentary amplitude values of the output signal; second sampling means for receiving the input signal to the device under test and the sampling signal to produce a second signal representing the momentary amplitude values of the input signal; first converting means for converting the first signal to first digital values; second converting means for converting the second signal to second digital values; processing means coupled to the first and second converting means for receiving the first and second digital values, and for calculating characteristics of the device under test from the first and second digital values.
Claim 3
Dependent Claim
39 words
The apparatus of claim 1 wherein the second generating means comprises a fractional N oscillator and a phase locked loop coupled to the fractional N oscillator for generating the sampling signal as an output of the phase locked loop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-21 | 1993-02-20 | 1993-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-21 | 1997-02-20 | 1997-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-21 | 2001-02-20 | 2001-08-22 | $7700.00 | Window Closed / Lapsed |