Semiconductor memory device comprising trench memory cells

Claim 2

A semiconductor memory device comprising: a semiconductor substrate, a plurality of word lines arranged on said semiconductor substrate, a plurality of bit lines arranged to intersect with said word lines, memory cells arranged at intersections of said word lines and said bit lines, said semiconductor substrate having cell trenches each formed in a region of each of said memory cells, a first isolation trench which is formed integrally with said cell trenches in adjacent memory cells in a direction parallel with said word lines, and a second isolation trench which is formed integrally with said cell trenches in adjacent memory cells in a direction parallel with said bit lines, each of said memory cells comprising a charge storage region formed in the inner surface of each of said cell trenches, and a switching transistor region provided between each of said bit lines and each of said charge storage regions, said switching transistor region utilizing a part of said word lines as a gate electrode, and isolation regions formed in the inner surfaces of said first and second isolation trenches; only portions of the bottom surface of said first isolation trench, between diagonally adjacent ones of said memory cells, containing said isolation regions.

Claim 3

A semiconductor memory device in accordance with claim 1, wherein each of said isolation regions comprises an insulating film.

Claim 4

A semiconductor memory device in accordance with claim 1, wherein each of said charge storage regions comprises an impurity diffusion layer, an insulating film formed on said impurity diffusion layer and a cell plate formed on said insulating film.

Claim 5

A semiconductor memory device comprising: a semiconductor substrate, a plurality of word lines arranged on said semiconductor substrate, a plurality of bit lines arranged to intersect with said word lines, memory cells arranged at intersections of said word lines and said bit lines, said semiconductor substrate having cell trenches each formed in a region of each of said memory cells, each of said cell trenches comprising a first trench and a second trench, a first isolation trench which is formed integrally with adjacent cell trenches in a direction parallel with said lines, and a second isolation trench which is formed integrally with said adjacent cell trenches in a direction parallel with said bit lines, each of said memory cells comprising a charge storage region formed on the inner surface of each of said cell trenches, and a switching transistor region provided between each of said bit lines and each of said charge storage regions, said switching transistor region utilizing a part of said word lines as a gate electrode, and isolation regions formed in the inner surfaces of said isolation trenches; only portions of the bottom surfaces of said isolation trenches, parallel to said word line between diagonally adjacent ones of said memory cells, containing said isolation regions.

Claim 6

A semiconductor memory device comprising: a semiconductor substrate, a plurality of word lines arranged on said semiconductor substrate, a plurality of bit lines arranged to intersect with said word lines, memory cells arranged at intersections of said word lines and said bit lines, said semiconductor substrate having cell trenches each formed in a region of each of said memory cells, each of said cell trenches comprising a first trench and a second trench, a first isolation trench which is formed integrally with adjacent cell trenches in a direction parallel with said lines, and a second isolation trench which is formed integrally with said adjacent cell trenches in a direction parallel with said bit lines, each of said memory cells comprising a charge storage region formed on the inner surface of each of said cell trenches, and a switching transistor region provided between each of said bit lines and each of said charge storage regions, said switching transistor region utilizing a part of said word lines as a gate electrode, and isolation regions formed in the inner surfaces of said isolation trenches; only portions of the bottom surfaces of said isolation trenches, parallel to said word line between diagonally adjacent ones of said memory cells, containing said isolation regions.

Claim 7

A semiconductor memory device in accordance with claim 4, wherein each of said isolation regions comprises an insulating film.

Claim 8

A semiconductor memory device in accordance with claim 4, wherein each of said charge storage regions comprises an impurity diffusion layer, an isulating film formed on said impurity diffusion layer and a cell plate formed on said insulating film.

Claim 9

A semiconductor memory device, comprising: a semiconductor substrate formed of a material of a first conductivity type and having a major surface; a plurality of word lines arranged on said semiconductor substrate; a plurality of bit lines arranged to intersect with said word lines; an array of memory cells on said substrate at intersections of said word lines and said bit lines; said major surface of said substrate having a cell trench formed among said memory cells and having isolation trenches formed integrally therein between memory cells of said array; charge storage regions of said cells formed in the surface of said cell trench; and isolating regions extending into the substrate, only portions of the bottom surfaces of said isolation trenches containing said isolating regions for electrically isolating charge storage layers or adjacent cells, including diagonally adjacent cells of the array, from each other.

Claim 10

A semiconductor memory device, comprising: a semiconductor substrate formed of a material of a first conductivity type and having a major surface; a plurality of word lines arranged on said semiconductor substrate; a plurality of bit lines arranged to intersect with said word lines; an array of memory cells on said substrate at intersections of said word lines and said bit lines; said major surface of said substrate having a cell trench formed among said memory cells and having isolation trenches formed integrally therein between memory cells of said array; charge storage regions of said cells formed in the surface of said cell trench; and isolating regions extending into the substrate, only portions of the bottom surfaces of said isolation trenches containing said isolating regions for electrically isolating charge storage layers or adjacent cells, including diagonally adjacent cells of the array, from each other.

Claim 11

The semiconductor memory device of claim 7, wherein said cell trench is formed in a staggered reticular pattern among said memory cells.

Claim 12

A semiconductor memory device in accordance with claim 7, wherein said isolation region comprises an insulating film.

Claim 13

A semiconductor memory device in accordance with claim 7, wherein each of said charge storage regions comprises an impurity diffusion layer, a cell plate, and an insulating film formed therebetween.