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US4859872A
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Synchronizing signal processing circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1988-03-23
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Granted: 1989-08-22
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Expires: 2008-03-23
Abstract
Abstract An input synchronizing signal is subjected to mean DC voltage adjustment so that the mean DC voltage thereof becomes a prescribed level. The input synchronizing signal after the mean DC voltage adjustment is compared with first reference voltage which is higher than the prescribed level and second reference voltage which is lower than the prescribed level by comparators, to derive an output synchronizing signal of constant polarity and amplitude or a polarity detection output for the input synchronizing signal.
Inventors
- 👤 Junichi Hyakutake
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:30
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H03; H03K; H03K5/00; H03K5/003; G; G01; G01R; G01R19/00; G01R19/165; G01R19/16566; G01R19/1659; H03K5/156
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
175 words
A synchronizing signal processing circuit comprising: mean DC voltage setting means for setting mean DC voltge of an input synchronizing signal at a prescribed level including a coupling capacitor for receiving said input synchronizing signal at its one end, and a voltage source connected to the other end of said coupling capacitor; and a window comparator having first reference voltage which is larger than said prescribed level and second reference voltage which is smaller than said prescribed level, for comparing the input synchronizing signal set by said main DC voltage setting means with said first reference voltage and said second reference voltage to output a signal of a first level when the input synchronizing signal set by said mean DC voltage setting means is in a level between said first reference voltage and said second reference voltage and a signal of a second level when it is in a level higher than said first reference voltage or lower than said second reference voltage, thereby an output synchronizing signal of constant polarity and amplitude is obtained.
Claim 2
Dependent Claim
175 words
A synchronizing signal processing circuit comprising: mean DC voltage setting means for setting mean DC voltge of an input synchronizing signal at a prescribed level including a coupling capacitor for receiving said input synchronizing signal at its one end, and a voltage source connected to the other end of said coupling capacitor; and a window comparator having first reference voltage which is larger than said prescribed level and second reference voltage which is smaller than said prescribed level, for comparing the input synchronizing signal set by said main DC voltage setting means with said first reference voltage and said second reference voltage to output a signal of a first level when the input synchronizing signal set by said mean DC voltage setting means is in a level between said first reference voltage and said second reference voltage and a signal of a second level when it is in a level higher than said first reference voltage or lower than said second reference voltage, thereby an output synchronizing signal of constant polarity and amplitude is obtained.
Claim 3
Dependent Claim
60 words
A synchronizing signal processing circuit in accordance with claim 1, wherein said window comparator comprises: a first comparator for comparing the input synchronizing signal set by said mean DC voltage setting means with said first reference voltage; and a second comparator for comparing the input synchronizing signal set by said mean DC voltage setting means with said second reference voltage.
Claim 4
Dependent Claim
107 words
A synchronizing signal processing circuit in accordance with claim 2, wherein said first comparator includes a first differential pair of transistors having bases to which the input synchronizing signal set by said mean DC voltage setting means and said first reference voltage are applied, respectively, and said second comparator includes a second differential pair of transistors having bases to which the input synchronizing signal set by said mean DC voltage setting means and said second reference voltage are applied, respectively, one collector of the second differential pair of transistors being coupled to one collector of said first differential pair of transistors to derive the output synchronizing signal.
Claim 5
Dependent Claim
113 words
A synchronizing signal processing circuit comprising: mean DC voltage setting means for setting mean DC voltage of an input synchronizing signal at a prescribed level; a first comparator having first reference voltage which is larger than said prescribed level, for comparing the input synchronizing signal set by said mean DC voltage setting means with said first reference voltage; a second comparator having second reference voltage which is smaller than said prescribed level, for comparing the input synchronizing signal set by said mean DC voltage setting means with said second reference voltage; and polarity detection means for detecting polarity of said input synchronizing signal based on comparison outputs from said first and second comparators.
Claim 6
Dependent Claim
113 words
A synchronizing signal processing circuit comprising: mean DC voltage setting means for setting mean DC voltage of an input synchronizing signal at a prescribed level; a first comparator having first reference voltage which is larger than said prescribed level, for comparing the input synchronizing signal set by said mean DC voltage setting means with said first reference voltage; a second comparator having second reference voltage which is smaller than said prescribed level, for comparing the input synchronizing signal set by said mean DC voltage setting means with said second reference voltage; and polarity detection means for detecting polarity of said input synchronizing signal based on comparison outputs from said first and second comparators.
Claim 7
Dependent Claim
44 words
A synchronizing signal processing circuit in accordance with claim 4, wherein said mean DC voltage setting means comprises: a coupling capacitor for receiving said input synchronizing signal at its one end; and a voltage source coupled to the other end of said coupling capacitor.
Claim 8
Dependent Claim
34 words
A synchronizing signal processing circuit in accordance with claim 5, wherein said polarity detection means includes voltage retention means for retaining a voltage level of said comparison outputs from said first and second comparators.
Claim 9
Dependent Claim
66 words
A synchronizing signal processing circuit in accordance with claim 6, wherein said voltage retention means comprises: a first diode for inputting a positive polarity output signal from said first comparator; a second diode for inputting a negative polarity output signal from said second comparator; time constant means for holding a voltage level of said positive or negative polarity output signal from said first or second diode.
Claim 10
Dependent Claim
44 words
A synchronizing signal processing circuit in accordance with claim 7, wherein said polarity detection means further includes means for outputting a prescribed level connected to said voltage retention means when there is no change in said comparison outputs from said first and second comparator.
Claim 11
Dependent Claim
48 words
A synchronizing signal processing circuit in accordance with claim 8, wherein said voltage retention means further comprises bias means connected to said time constant means for biasing said time constant means to hold a prescribed voltage level when there is no signal from said first and second diodes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-21 | 1993-02-20 | 1993-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-21 | 1997-02-20 | 1997-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-21 | 2001-02-20 | 2001-08-22 | $7700.00 | Window Closed / Lapsed |