Digital waveform conditioning circuit

Claim 2

A digital waveform conditioning circuit which comprises: an input terminal for receiving a signal deformed from a digital rectangular signal, said deformed digital signal having alternating positive and negative cycles; means for generating a reference signal produced by combining positive and negative components rectified from the positive and negative cycles of the deformed digital signal; means for comparing said deformed digital signal with said reference signal; means for holding an output signal of said comparing means for a period controlled by a clock signal synchronizing said output signal of said holding means with said digital rectangular signal; and an output terminal for receiving the output signal from said holding means.

Claim 3

A digital waveform conditioning circuit according to claim 1, wherein said holding means includes inverted and non-inverted outputs with one of said outputs connected to said output terminal and wherein said reference signal generating means comprises: individual means for sampling the positive and negative cycles of said deformed digital signals under the control of said inverted and non-inverted outputs of said holding means.

Claim 4

A digital waveform conditioning circuit according to claim 2, wherein said individual sampling means comprise first and second analog switching means, each having a pair of main current-carrying terminals and a control terminal, the control terminals being individually connected to different ones of said inverted and non-inverted outputs; and wherein said reference signal generating means further comprises: first and second diodes connected between said input terminal and individual ones of said pair of current-carrying terminals, said diodes being connected in opposite polarity to said input terminal; first and second capacitors individually connected between the other ones of said pair of current-carrying terminals and ground for storing voltages applied by said first and second analog switching means; and first and second resistors each having one terminal connected to individual ones of said capacitors and the other terminals connected together for combining voltages stored on said first and second capacitors, said combined voltages forming said reference signal.

Claim 5

A digital waveform conditioning circuit according to any one of claims 1 to 3, wherein said holding means is a D type flip-flop.

Claim 6

A digital waveform conditioning circuit which comprises: an input terminal for receiving a signal deformed from a digital rectangular signal, said deformed digital signal having alternating positive and negative cycles; means for rectifying said deformed signal; means connected to said rectifying means for generating a reference signal produced by combining positive and negative components rectified from the positive and negative cycles of the deformed digital signal; means for comparing said deformed digital signal with said reference signal; means for holding an output signal of said comparing means for a period controlled by a clock signal synchronizing said output signal of said holding means with said digital rectangular signal; and an output terminal for receiving the output signal from said holding means.

Claim 7

A digital waveform conditioning circuit which comprises: an input terminal for receiving a signal deformed from a digital rectangular signal, said deformed digital signal having alternating positive and negative cycles; means for rectifying said deformed signal; means connected to said rectifying means for generating a reference signal produced by combining positive and negative components rectified from the positive and negative cycles of the deformed digital signal; means for comparing said deformed digital signal with said reference signal; means for holding an output signal of said comparing means for a period controlled by a clock signal synchronizing said output signal of said holding means with said digital rectangular signal; and an output terminal for receiving the output signal from said holding means.

Claim 8

A digital waveform conditioning circuit according to claim 5, wherein said holding means includes inverted and non-inverted outputs with one of said outputs connected to said output terminal and wherein said reference signal generating means comprises; individual means for sampling the positive and negative cycles of said deformed digital signals under the control of said inverted and non-inverted outputs of said holding means.

Claim 9

A digital waveform conditioning circuit according to claim 6: wherein said individual sampling means comprise first and second analog switching means, each having a pair of main current-carrying terminals and a control terminal, the control terminals being individually connected to different ones of said inverted and non-inverted outputs; wherein said rectifying means comprises first and second diodes connected between said input terminal and individual ones of said pair of current-carrying terminals, said diodes being connected in opposite polarity to said input terminal; and wherein said reference signal generating means further comprises: first and second capacitors individually connected between the other ones of said pair of current-carrying terminals and ground for storing voltages applied by said first and second analog switching means; and first and second resistors each having one terminal connected to individual ones of said capacitors and the other terminals connected together for combining voltages stored on said first and second capacitors, said combined voltages forming said reference signal.

Claim 10

A digital waveform conditioning circuit according to any one of claims 5 to 7, wherein said holding means is a D type flip-flop.