Circuit for processing a digital signal

Claim 1

In a circuit for processing a useful signal which varies in amplitude between positive and negative values about a zero value and contains information in the locations of its zero passages, which circuit includes: a zero passage detector having an input; a first capacitor connected in series between a source of the useful signal and the detector input for supplying a signal representative of the useful signal; and means for coupling, at the detector input, the signal representative of the useful signal with a first clamping potential only during the positive value intervals of the signal representative of the useful signal and with a second clamping potential only during the negative intervals of the signal representative of the useful signal, the improvement wherein said circuit further comprises a source of the first clamping potential and a source of the second clamping potential, and said signal coupling means comprise: a first controllable switch connected to said source of the first clamping potential for selectively coupling the first clamping potential with the signal representative of the useful signal; a second controllable switch connected to said source of the second clamping potential for selectively coupling the second clamping potential with the signal representative of the useful signal; and control pulse generating means connected for applying to each said switch control pulses derived from the signal representative of the useful signal and having a timing such that said first switch is closed for a predetermined period during each positive value interval of the signal representative of the useful signal and said second switch is closed for a predetermined period during each negative value interval of the signal representative of the useful signal, with the predetermined closing period of each said switch being determined by the duration of the control pulses applied thereto.