Voltage level setting circuit

Claim 2

A voltage level setting circuit for setting a D.C. voltage level of a predetermined portion of an input signal received through a coupling capacitor to a desired reference voltage level suited for a signal processing which is carried out in a signal processing circuit, said voltage level of the predetermined portion being used as a reference level of said input signal, said voltage level setting circuit, comprising: a charge injecting circuit for injecting a quantity of charge to a node between said coupling capacitor and said signal processing circuit, wherein said node has a bias voltage during a predetermined time period, and wherein said voltage substantially corresponds to the predetermined portion of said input signal; and control means for controlling the injection of charge by said charge injecting circuit responsive to a signal from said signal processing circuit so that the D.C. voltage level of the predetermined portion at said node is set to said desired reference voltage level.

Claim 3

A voltage level setting circuit as claimed in claim 1 in which said control means controls said charge injecting circuit so that said charge injecting circuit is electrically disconnected from said node during a time period corresponding to a portion other than the predetermined portion of said input signal.

Claim 4

A voltage level setting circuit as claimed in claim 1 in which said control means comprises a first circuit for comparing a voltage level of the input signal received through said node during a predetermined time period corresponding to said predetermined portion and said desired reference voltage level and for producing an error voltage dependent on a voltage difference between the two compared voltages, and a second circuit for producing a first current responsive to said error voltage when the voltage level of said predetermined portion is less than said desired reference voltage level and said error voltage is greater than zero and for producing a second current responsive to said error voltage when the voltage level of said predetermined portion is greater than said desired reference voltage level and said error voltage is less than zero, said charge injecting circuit injecting a quantity of positive charge to said node to raise the voltage level at said node responsive to said first current and injecting a quantity of negative charge to said node to lower the voltage level at said node responsive to said second current.

Claim 5

A voltage level setting circuit as claimed in claim 1 in which said input signal is an image signal, said predetermined portion being a synchronizing signal period of said image signal.

Claim 6

A voltage level setting circuit as claimed in claim 1 in which said control means comprises means for obtaining a digital error signal by comparing an output digital signal corresponding to said desired reference voltage level and means for controlling said charge injecting circuit based on said digital error signal.

Claim 7

A voltage level setting circuit for setting a D.C. voltage level of a predetermined portion of an input signal received through a coupling capacitor to a desired reference voltage level suited for a signal processing which is carried out in a signal processing circuit, said voltage level of the predetermined portion being used as a reference level of said input signal, said voltage level setting circuit, comprising: a charge injecting circuit for injecting a quantity of charge to a node between said coupling capacitor and said signal processing circuit; control means for controlling the injection of charge by said charge injecting circuit responsive to a signal from said signal processing circuit so that the D.C. voltage level of the predetermined portion at said node is set to said desired reference voltage level; and switching means for connecting said node to a bias voltage during a predetermined time period corresponding to the predetermined portion of said input signal and for disconnecting said node from said bias voltage during a time period corresponding to a portion other than said predetermined portion, said bias voltage being set approximately equal to said desired reference voltage level, wherein said control means comprises a first circuit for comparing a voltage level of the input signal received through said node during a predetermined time period corresponding to said predetermined portion and said desired reference voltage level and for producing an error voltage dependent on a voltage difference between the two compared voltages, and a second circuit for producing a first current responsive to said error voltage when the voltage level of said predetermined portion is less than said desired reference voltage level and said error voltage is greater than zero and for producing a second current responsive to said error voltage when the voltage level of said predetermined portion is greater than said desired reference voltage level and said error voltage is less than zero, wherein said charge injecting circuit injecting a quantity of positive charge to said node to raise the voltage level at said node responsive to said first current and injecting a quantity of negative charge to said node to lower the voltage level at said node responsive to said second current.

Claim 8

A voltage level setting circuit for setting a D.C. voltage level of a predetermined portion of an input signal received through a coupling capacitor to a desired reference voltage level suited for a signal processing which is carried out in a signal processing circuit, said voltage level of the predetermined portion being used as a reference level of said input signal, said voltage level setting circuit, comprising: a charge injecting circuit for injecting a quantity of charge to a node between said coupling capacitor and said signal processing circuit; control means for controlling the injection of charge by said charge injecting circuit responsive to a signal from said signal processing circuit so that the D.C. voltage level of the predetermined portion at said node is set to said desired reference voltage level; and switching means for connecting said node to a bias voltage during a predetermined time period corresponding to the predetermined portion of said input signal and for disconnecting said node from said bias voltage during a time period corresponding to a portion other than said predetermined portion, said bias voltage being set approximately equal to said desired reference voltage level, wherein said control means comprises a first circuit for comparing a voltage level of the input signal received through said node during a predetermined time period corresponding to said predetermined portion and said desired reference voltage level and for producing an error voltage dependent on a voltage difference between the two compared voltages, and a second circuit for producing a first current responsive to said error voltage when the voltage level of said predetermined portion is less than said desired reference voltage level and said error voltage is greater than zero and for producing a second current responsive to said error voltage when the voltage level of said predetermined portion is greater than said desired reference voltage level and said error voltage is less than zero, wherein said charge injecting circuit injecting a quantity of positive charge to said node to raise the voltage level at said node responsive to said first current and injecting a quantity of negative charge to said node to lower the voltage level at said node responsive to said second current.

Claim 9

A voltage level setting circuit as claims in claim 6, wherein said control means is for controlling said charge injecting circuit so that said charge injecting circuit is electrically disconnected from said node during a time period corresponding to a portion other than the predetermined portion of said input signal.

Claim 10

A voltage level setting circuit as claimed in claim 6, wherein said input signal is an image signal, and wherein said predetermined portion being a synchronously signal period of said image signal.

Claim 11

A voltage level setting circuit for setting a D.C. voltage level of a predetermined portion of an input signal received through a coupling capacitor to a desired reference voltage level suited for a signal processing which is carried out in a signal processing circuit, said voltage level of the predetermined portion being used as a reference level of said input signal, said voltage level setting circuit, comprising: a charge injecting circuit for injecting a quantity of charge to a node between said coupling capacitor and said signal processing circuit; and control means for controlling the injection of charge by said charge injecting circuit responsive to a signal from said signal processing circuit so that the D.C. voltage level of the predetermined portion at said node is set to said desired reference voltage level, wherein said control means comprises a plurality of capacitors, first switching means for selectively connecting each first terminal of said capacitor to at least one of first and second constant voltages, and second switching means for selectively connecting each second terminal of said capacitors to at least one of said node and said second constant voltage, said control means controlling switching of said first and second switching means.

Claim 12

A voltage level setting circuit for setting a D.C. voltage level of a predetermined portion of an input signal received through a coupling capacitor to a desired reference voltage level suited for a signal processing which is carried out in a signal processing circuit, said voltage level of the predetermined portion being used as a reference level of said input signal, said voltage level setting circuit, comprising: a charge injecting circuit for injecting a quantity of charge to a node between said coupling capacitor and said signal processing circuit; and control means for controlling the injection of charge by said charge injecting circuit responsive to a signal from said signal processing circuit so that the D.C. voltage level of the predetermined portion at said node is set to said desired reference voltage level, wherein said control means comprises a plurality of capacitors, first switching means for selectively connecting each first terminal of said capacitor to at least one of first and second constant voltages, and second switching means for selectively connecting each second terminal of said capacitors to at least one of said node and said second constant voltage, said control means controlling switching of said first and second switching means.

Claim 13

A voltage level setting circuit as claimed in claim 9 in which said capacitors have mutually different capacitances such that an arbitrary capacitor C i has a capacitance 2 i-1 ×C i+1 , where i is an integer.

Claim 14

A voltage level setting circuit as claimed in claim 9 which further comprises switching means for connecting said node to a bias voltage during a predetermined time period corresponding to the predetermined portion of said input signal and for disconnecting said node from said bias voltage during a time period corresponding to a portion other than said predetermined portion, said bias voltage being set approximately equal to said desired reference voltage level.

Claim 15

A voltage level setting circuit as claimed in claim 9, wherein said control means is for controlling said charge injecting circuit so that said charge injecting circuit is electrically disconnected from said node during a time period corresponding to a portion other than the predetermined portion of said input signal.

Claim 16

A voltage level setting circuit as claimed in claim 9, wherein said input signal is an image signal, wherein said predetermined portion being a synchronizing signal period of said image signal.

Claim 17

A voltage level setting circuit for setting a D.C. voltage level of a predetermined portion of an input signal received through a coupling capacitor to a desired reference voltage level suited for a signal processing which is carried out in a signal processing circuit, said voltage level of the predetermined portion being used as a reference level of said input signal, said voltage level setting circuit, comprising: a charge injecting circuit for injecting a quantity of charge to a node between said coupling capacitor and said signal processing circuit; control means for controlling the injection of charge by said charge injecting circuit responsive to a signal from said signal processing circuit so that the D.C. voltage level of the predetermined portion at said node is set to said desired reference voltage level; and switching means for connecting said node to a bias voltage during a predetermined time period corresponding to the predetermined portion of said input signal and for disconnecting said node from said bias voltage during a time period corresponding to a portion other than said predetermined portion, said bias voltage being set approximately equal to said desired reference voltage level.

Claim 18

A voltage level setting circuit for setting a D.C. voltage level of a predetermined portion of an input signal received through a coupling capacitor to a desired reference voltage level suited for a signal processing which is carried out in a signal processing circuit, said voltage level of the predetermined portion being used as a reference level of said input signal, said voltage level setting circuit, comprising: a charge injecting circuit for injecting a quantity of charge to a node between said coupling capacitor and said signal processing circuit; control means for controlling the injection of charge by said charge injecting circuit responsive to a signal from said signal processing circuit so that the D.C. voltage level of the predetermined portion at said node is set to said desired reference voltage level; and switching means for connecting said node to a bias voltage during a predetermined time period corresponding to the predetermined portion of said input signal and for disconnecting said node from said bias voltage during a time period corresponding to a portion other than said predetermined portion, said bias voltage being set approximately equal to said desired reference voltage level.

Claim 19

A voltage setting circuit as claimed in claim 14, wherein said input signal is an image signal, wherein said predetermined portion being a synchronizing signal period of said image signal.

Claim 20

A voltage level setting circuit for setting a voltage level of a predetermined portion of an input signal received from a signal source circuit system to a desired reference voltage level suited for a signal processing which is carried out in a signal processing circuit system, said voltage level of the predetermined portion being used as a reference level of said input signal, said voltage level setting circuit, comprising: comparing means for comparing a digital signal corresponding to said input voltage from said signal processing circuit system and a digital signal corresponding to said desired reference voltage level and for outputting a digital error voltage dependent on a voltage difference between digital quantities of the two compared digital signals; digital-to-analog converter means for converting the digital error voltage from said comparing means into an analog error voltage; circuit means for substantially adding the analog error voltage from said digital-to-analog converter means to said input signal during a predetermined time period corresponding to said predetermined portion of said input signal; and switching means for connecting a node between a coupling capacitor and said signal processing circuit system to a bias voltage during a predetermined time period corresponding to the predetermined portion of said input signal and for disconnecting said node from said bias voltage during a time period corresponding to a portion other than said predetermined portion, said input signal being received from said signal source circuit system through said coupling capacitor, said bias voltage being set approximately equal to said desired reference voltage level.

Claim 21

A voltage level setting circuit for setting a voltage level of a predetermined portion of an input signal received from a signal source circuit system to a desired reference voltage level suited for a signal processing which is carried out in a signal processing circuit system, said voltage level of the predetermined portion being used as a reference level of said input signal, said voltage level setting circuit, comprising: comparing means for comparing a digital signal corresponding to said input voltage from said signal processing circuit system and a digital signal corresponding to said desired reference voltage level and for outputting a digital error voltage dependent on a voltage difference between digital quantities of the two compared digital signals; digital-to-analog converter means for converting the digital error voltage from said comparing means into an analog error voltage; circuit means for substantially adding the analog error voltage from said digital-to-analog converter means to said input signal during a predetermined time period corresponding to said predetermined portion of said input signal; and switching means for connecting a node between a coupling capacitor and said signal processing circuit system to a bias voltage during a predetermined time period corresponding to the predetermined portion of said input signal and for disconnecting said node from said bias voltage during a time period corresponding to a portion other than said predetermined portion, said input signal being received from said signal source circuit system through said coupling capacitor, said bias voltage being set approximately equal to said desired reference voltage level.

Claim 22

A voltage level setting circuit as claimed in claim 16 in which said circuit means comprises an integrator for integrating said analog error voltage from said digital-to-analog converter means, and an analog adder for substantially adding an output voltage of said integrator to said input voltage.

Claim 23

A voltage level setting circuit as claimed in claim 16 in which said input signal is an image signal, said predetermined portion being a synchronizing signal period of said image signal.

Claim 24

A voltage level setting circuit for setting a D.C. voltage level of a predetermined portion of an input signal received through a coupling capacitor to a desired reference voltage level suited for a signal processing which is carried out in a signal processing circuit, said voltage level of the predetermined portion being used as a reference level of said input signal, said voltage level setting circuit, comprising: a charge injecting circuit for injecting a quantity of charge to a node between said coupling capacitor and said signal processing circuit; and control means for controlling the injection of charge by said charge injecting circuit responsive to a signal from said signal processing circuit so that the D.C. voltage level of the predetermined portion at said node is set to said desired reference voltage level, said control means controlling said charge injecting circuit so that said charge injecting circuit is electrically disconnected from said node during a time period corresponding to a portion other than the predetermined portion of said input signal, wherein said charge injecting circuit comprising a positive charge injecting circuit and a negative charge injecting circuit which respectively inject a predetermined quantity of charge regardless of a voltage at said node, and wherein said control means is for selectively connecting said positive charge injecting circuit and said negative charge injecting circuit to said node.

Claim 25

A voltage level setting circuit for setting a D.C. voltage level of a predetermined portion of an input signal received through a coupling capacitor to a desired reference voltage level suited for a signal processing which is carried out in a signal processing circuit, said voltage level of the predetermined portion being used as a reference level of said input signal, said voltage level setting circuit, comprising: a charge injecting circuit for injecting a quantity of charge to a node between said coupling capacitor and said signal processing circuit; and control means for controlling the injection of charge by said charge injecting circuit responsive to a signal from said signal processing circuit so that the D.C. voltage level of the predetermined portion at said node is set to said desired reference voltage level, said control means controlling said charge injecting circuit so that said charge injecting circuit is electrically disconnected from said node during a time period corresponding to a portion other than the predetermined portion of said input signal, wherein said charge injecting circuit comprising a positive charge injecting circuit and a negative charge injecting circuit which respectively inject a predetermined quantity of charge regardless of a voltage at said node, and wherein said control means is for selectively connecting said positive charge injecting circuit and said negative charge injecting circuit to said node.